參數(shù)資料
型號(hào)： ATF1508BE-7AU100
廠(chǎng)商： Atmel
文件頁(yè)數(shù)： 29/30頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 128MC 1.8V ISP 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： ATF15xx
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 1.7 V ~ 1.9 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 80
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤(pán)
8
3663A–PLD–1/08
ATF1508BE
1.6
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
1.7
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to all 16 macrocells within the logic block. The foldback is an inverse polarity of one
of the macrocell’s product terms. The 16 foldback terms in each logic block allow generation of
high fan-in sum terms or other complex logic functions with little additional delay.
2.
Input and I/O Pins
2.1
Programmable Pin-keeper Option for Inputs and I/Os
The ATF1508BE offers the option of individually programming each of its input or I/O pin so that
pin-keeper circuit can be utilized. When any pin is driven high or low and then subsequently left
floating, it will stay at that previous high or low level. This circuitry prevents undriven input and
I/O lines from floating to intermediate voltage levels, which causes unnecessary power con-
sumption and system noise. The keeper circuits eliminate the need for external pull-up resistors
and eliminate their DC power consumption.
Figure 2-1 shows the pin-keeper circuit for an Input Pin and Figure 2-2 shows the same for an
I/O pin. The pin-keeper circuit is a weak feedback latch and has an effective resistance that is
approximately 50 k
.
Figure 2-1.
Input with Programmable Pin-keeper
50K
VCCINT
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