參數(shù)資料
型號(hào): ATF1504BE-7AU44
廠商: Atmel
文件頁(yè)數(shù): 27/30頁(yè)
文件大?。?/td> 0K
描述: IC CPLD 64MC 1.8V 44-TQFP
標(biāo)準(zhǔn)包裝: 160
系列: ATF15xx
可編程類型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 1.7 V ~ 1.9 V
宏單元數(shù): 64
輸入/輸出數(shù): 32
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 608 (CN2011-ZH PDF)
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
6
3637B–PLD–1/08
ATF1504BE
Figure 1-4.
ATF1504BE Macrocell
1.1
Product Terms and Select Mux
Each ATF1504BE macrocell has five product terms. Each product term receives as its inputs all
signals from the switch matrix and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX configuration is determined by the design
compiler, which selects the optimum macrocell configuration.
1.2
OR/XOR/CASCADE Logic
The ATF1504BE’s logic structure is designed to efficiently support all types of logic. Within a sin-
gle macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with minimal additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selec-
tion. For registered functions, the fixed levels allow DeMorgan minimization of product terms.
SCHMITT
TRIGGER
SSTL
BURIED FEEDBACK
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