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參數(shù)資料
| 型號(hào)： | ATF1500ASV-15AC100 |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | Low-voltage, Complex Programmable Logic Device |
| 中文描述： | EE PLD, 15 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/29頁 |
| 文件大?。?/td> | 314K |
| 代理商： | ATF1500ASV-15AC100 |
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1
Features
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
– 3.0 to 3.6V Operating Range
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
–
D/T/Latch Configurable Flip-flops
–
Global and Individual Register Control Signals
–
Global and Individual Output Enable
–
Programmable Output Slew Rate
–
Programmable Output Open-collector Option
–
Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
–
Automatic 5 μA Standby for
“
L
”
Version
–
Pin-controlled 100 μA Standby Mode (Typical)
–
Programmable Pin-keeper Circuits on Inputs and I/Os
–
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
–
100% Tested
–
Completely Reprogrammable
–
10,000 Program/Erase Cycles
–
20 Year Data Retention
–
2000V ESD Protection
–
200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable
“
Pin-keeper
”
Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
–
Edge-controlled Power-down
“
L
”
–
Individual Macrocell Power Option
–
Disable ITD on Global Clocks, Inputs and I/O
Low-voltage,
Complex
Programmable
Logic Device
ATF1504ASV
ATF1504ASVL
Rev. 1409I
–
PLD
–
2/03
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