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參數(shù)資料
| 型號： | AT9933LG-G |
| 廠商： | SUPERTEX INC |
| 元件分類： | 穩(wěn)壓器 |
| 中文描述： | SWITCHING CONTROLLER, PDSO8 |
| 封裝： | 4.90 X 3.90 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, GREEN, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 505K |
| 代理商： | AT9933LG-G |
5
AT9933
Supertex inc.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
Power Topology
The AT9933 is optimized to drive a continuous conduction
mode (CCM) boost-buck DC/DC converter topology com-
monly referred to as “uk converter” (see Circuit Diagram
on page 1). This power converter topology offers numerous
advantages useful for driving high-brightness light emitting
diodes (HB LED). These advantages include step-up or
step-down voltage conversion ratio and low input and output
current ripple. The output load is decoupled from the input
voltage with a capacitor making the driver inherently failure-
safe for the output load.
The AT9933 offers a simple and effective control technique
for use with a boost-buck LED driver. It uses two hysteretic
mode controllers – one for the input and one for the output.
The outputs of these two hysteretic comparators are AND-
ED and used to drive the external FET. This control scheme
gives accurate current control and constant output current in
the presence of input voltage transients without the need for
complicated loop design.
Input Voltage Regulator
The AT9933 can be powered directly from its VIN pin that
takes a voltage up to 75V. When a voltage is applied at the
VIN pin, the AT9933 seeks to regulate a constant 7.5V (typ)
at the VDD pin. The regulator also has a built in under-volt-
age lockout which shuts off the IC if the voltage at the VDD
pin falls below the UVLO threshold.
The VDD pin must be bypassed by a low ESR capacitor
(≥0.1μF) to provide a low impedance path for the high fre-
quency current of the output gate driver.
The input current drawn from the V
pin is a sum of the 1mA
current drawn by the internal circuit and the current drawn
by the gate driver (which in turn depends on the switching
frequency and the gate charge of the external FET).
I
IN
= 1.0mA + Q
G
f
S
(1)
In the above equation, f
is the switching frequency and Q
G
is the gate charge of the external FET (which can be ob-
tained from the datasheet of the FET).
Minimum Input Voltage at VIN pin
The minimum input voltage at which the converter will start
and stop depends on the minimum voltage drop required for
the linear regulator. The internal linear regulator will regulate
the voltage at the VDD pin when V
is between 8.0 and 75V.
However, when V
is less than 8.0V, the converter will still
function as long as V
is greater than the under voltage
lockout. Thus, under certain conditions, the converter will be
able to start at V
IN
voltages of less than 8.0V. The start/stop
voltages at the VIN pin can be determined using the maxi-
mum voltage drop across the linear regulator as a function
of the current drawn. This data is shown in Fig. 1 for ambient
temperatures of 25oC and 125oC.
Assume an ambient temperature of 125°C. Assuming the IC
is driving a 15nC gate charge FET at 300kHz, the total input
current is estimated to be 5.5mA (using Eqn. 1). At this input
current, the maximum voltage drop from Fig. 1 can be ap-
proximately estimated to be V
= 2.7V. However, before
the IC starts switching the current drawn will be 1.0mA. At
this current level, the voltage drop is approximately V
=
0.5V. Thus, the start/stop V
IN
voltages can be computed to
be:
V
IN-START
= UVLO
MAX
+ V
DROP1
= 6.95V + 0.5V
= 7.45V
V
IN-STOP
= UVLO
MAX
- ΔUVLO + V
DROP
= 6.95 - 0.5V + 2.7V
= 9.15V
Note that in this case, since the gate drive draws too much
current, V
is less than V
. In such cases, the con-
trol IC will oscillate between on and off if the input voltage is
between the start and stop voltages. In these circumstances,
it is recommended that the input voltage be kept higher than
V
(in this case the IC will operate normally if the input
voltage is kept higher than 9.2V).
In case of input transients that reduce the input voltage be-
low 8.0V (like cold crank condition in an automotive system),
the VIN pin of the AT9933 can be connected to the drain of
the MOSFET through a switching diode with a small (1.0nF)
capacitor between VIN and GND (as long as the drain volt-
age does not exceed 75V). Since the drain of the FET is at
a voltage equal to the sum of the input and output voltages,
the IC will still be operational when the input goes below 8V.
In these cases, a larger capacitor is needed to the VDD pin
to supply power to the IC when the MOSFET is on.
Functional Description
Voltage Drop vs. I
IN
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 1 2 3 4 5 6 7
I
IN
(mA)
V
Fig. 1. Maximum Voltage Drop vs. Input Current
125
O
C
25
O
C
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