參數(shù)資料
型號： AT9933LG-G
廠商： SUPERTEX INC
元件分類： 穩(wěn)壓器
中文描述： SWITCHING CONTROLLER, PDSO8
封裝： 4.90 X 3.90 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, GREEN, MS-012AA, SOIC-8
文件頁數(shù)： 2/9頁
文件大?。?/td> 505K
代理商： AT9933LG-G
2
AT9933
Supertex inc.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
Ordering Information
Device
8-Lead SOIC
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
AT9933
AT9933LG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
Value
V
IN
to GND
CS1, CS2, PWMD, GATE to GND
-0.5V to +75V
-0.3V to (V
DD
+ 0.3V)
V
DD(MAX)
Continuous Power Dissipation
(T
A
= +25°C)
12V
8-Pin SOIC
700mW
Junction temperature
+150°C
Storage temperature range
-65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Pin Configuration
8 REF
7 CS2
6 VDD
5 PWMD
VIN 1
CS1 2
GND 3
GATE 4
Sym
Parameter
Min
Typ
Max
Units
Conditions
Input
V
INDC
Input DC supply voltage range
1
*
(2)
-
75
V
DC input voltage
I
INSD
Shut-down mode supply current
1
-
-
0.5
1.0
mA
PWMD connected to GND,
V
IN
= 12V
Internal Regulator
V
DD
Internally regulated voltage
*
7.0
7.5
9.0
V
V
= 8 - 75V, I
= 0,
500pF capacitor at GATE,
PWMD = GND
UVLO
V
DD
undervoltage lockout threshold
*
6.35
6.70
7.05
V
V
DD
rising
UVLO
V
DD
undervoltage lockout hysteresis
-
-
500
-
mV
---
Notes:
1. Also limited by package power dissipation limit, whichever is lower.
2. Depends on the current drawn by the part - see application section.
* Specifications apply over the full operating ambient temperature range of -40oC < T
A
< +125oC. Guaranteed by design and characterization.
Electrical Characteristics
(Specifications are at T
A
= 25°C. V
IN
= Open, V
DD
= 7.5V unless otherwise noted)
Thermal Resistance
Package
θ
ja
8-Lead SOIC
128
O
C/W
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YWW
9933
LLLL
Product Marking
8-Lead SOIC (LG)
8-Lead SOIC (LG)
(top view)
Package may or may not include the following marks: Si or
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