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6384DS–ATARM–13-Jan-10
AT91SAM9G20 Summary
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap
Boot Mode Select
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
Allows Handling of Dynamic Exception Vectors
7.2.1
Matrix Masters
The Bus Matrix of the AT91SAM9G20 manages six Masters, which means that each master can
perform an access concurrently with others, according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
7.2.2
Matrix Slaves
Each Slave has its own arbiter, thus allowing to program a different arbitration per Slave.
Table 7-1.
List of Bus Matrix Masters
Master 0
ARM926 Instruction
Master 1
ARM926 Data
Master 2
PDC
Master 3
ISI Controller
Master 4
Ethernet MAC
Master 5
USB Host DMA
Table 7-2.
List of Bus Matrix Slaves
Slave 0
Internal SRAM0 16 KBytes
Slave 1
Internal SRAM1 16 KBytes
Slave 2
Internal ROM
USB Host User Interface
Slave 3
External Bus Interface
Slave 4
Internal Peripherals
