參數(shù)資料
型號: AT91SAM9G20B-CU
廠商: Atmel
文件頁數(shù): 6/42頁
文件大?。?/td> 0K
描述: IC ARM9 MPU 217-LFBGA
產(chǎn)品培訓模塊: SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
標準包裝: 126
系列: SAM9G
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 400MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,ISI,MMC,SPI,SSC,UART/USART,USB
外圍設備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: ROM
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 1.1 V
數(shù)據(jù)轉換器: A/D 4x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 217-LFBGA
包裝: 托盤
配用: AT91SAM9G20-EK-ND - KIT EVAL FOR AT91SAM9G20 MCU
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
其它名稱: AT91SAM9G20-CU
AT91SAM9G20-CU-ND
14
6384DS–ATARM–13-Jan-10
AT91SAM9G20 Summary
6.
I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 k
Ω to GND, so that it can be left uncon-
nected for normal operations.
The NTRST signal is described in the Reset Pins paragraph.
All the JTAG signals are supplied with VDDIOP.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 k
Ω to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 k
Ω minimum to
VDDIOP.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers inte-
grate a programmable pull-up resistor of 75 k
Ωtypical with the exception of P4 - P31. For details,
refer to the section “AT91SAM9G20 Electrical Characteristics”. Programming of this pull-up
resistor is performed independently for each I/O line through the PIO Controllers.
6.5
I/O Line Drive Levels
The PIO lines drive current capability is described in the DC Characteristics section of the prod-
uct datasheet.
6.6
Shutdown Logic Pins
The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is
no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1
M
Ω. The resisitor value is calculated according to the regulator enable implementation and the
SHDN level.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
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