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參數(shù)資料
| 型號： | AT91SAM7XC256-CU-999 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 35/47頁 |
| 文件大小： | 0K |
| 描述： | IC MCU ARM7 256KB FLASH 100TFBGA |
| 產(chǎn)品培訓(xùn)模塊： | SAM9 MPU Boot Solutions & Application Deployment AT91SAM7X and SAM7XC Flash-based Microcontrollers MCU Product Line Introduction |
| 標準包裝： | 3,000 |
| 系列： | SAM7XC |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 55MHz |
| 連通性： | CAN，以太網(wǎng)，I²C，SPI，SSC，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 62 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TFBGA |
| 包裝： | 帶卷 (TR) |
| 配用： | AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9 AT91SAM7XC-EK-ND - KIT EVAL FOR AT91SAM7XC256/128 |
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6209DS–ATARM–17-Feb-09
AT91SAM7XC512/256/128
– Counter (CTR)
8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode
Last Output Data Mode allowing Message Authentication Code (MAC) generation
Hardware Countermeasures against Differential Power Analysis attacks
Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
10.16 Triple Data Encryption Standard
Single Data Encryption Standard (DES) and Triple Data Encryption
Algorithm (TDEA or TDES) supports
Compliant with FIPS Publication 46-3, Data Encryption Standard (DES)
64-bit Cryptographic Key
Two-key or Three-key Algorithms
18-clock Cycles Encryption/Decryption Processing Time for DES
50-clock Cycles Encryption/Decryption Processing Time for TDES
Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES
Modes of Operation:
– Electronic Codebook (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
8-, 16-, 32- and 64- Data Sizes Possible in CFB Mode
Last Output Data Mode allowing Optimized Message (Data) Authentication Code (MAC)
generation
Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
10.17 Analog-to-Digital Converter
8-channel ADC
10-bit 384 Ksamples/sec. Successive Approximation Register ADC
±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity
Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
External voltage reference for better accuracy on low voltage inputs
Individual enable and disable of each channel
Multiple trigger sources
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
Sleep Mode and conversion sequencer
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