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6175H–ATARM–03-Dec-07
AT91SAM7S Series Preliminary
8.8
Embedded Flash
8.8.1
Flash Overview
The Flash of the AT91SAM7S512 is organized in two banks (dual plane) of 1024 pages of
256 bytes. The 524,288 bytes are organized in 32-bit words.
The Flash of the AT91SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The
262,144 bytes are organized in 32-bit words.
The Flash of the AT91SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The
131,072 bytes are organized in 32-bit words.
The Flash of the AT91SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The
65,536 bytes are organized in 32-bit words.
The Flash of the AT91SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes.
The 32,768 bytes are organized in 32-bit words.
The Flash of the AT91SAM7S161/16 is organized in 256 pages (single plane) of 64 bytes.
The 16,384 bytes are organized in 32-bit words.
The Flash of the AT91SAM7S512/256/128 contains a 256-byte write buffer, accessible
through a 32-bit interface.
The Flash of the AT91SAM7S64/321/32/161/16 contains a 128-byte write buffer, accessible
through a 32-bit interface.
The Flash benefits from the integration of a power reset cell and from the brownout detector.
This prevents code corruption during power supply changes, even in the worst conditions.
When Flash is not used (read or write access), it is automatically placed into standby mode.
8.8.2
Embedded Flash Controller
The Embedded Flash Controller (EFC) manages accesses performed by the masters of the sys-
tem. It enables reading the Flash and writing the write buffer. It also contains a User Interface,
mapped within the Memory Controller on the APB. The User Interface allows:
starting commands such as full erase, page erase, page program, NVM bit set, NVM bit
clear, etc.
getting the end status of the last command
getting error status
programming interrupts on the end of the last commands or on errors
The Embedded Flash Controller also provides a dual 32-bit prefetch buffer that optimizes 16-bit
access to the Flash. This is particularly efficient when the processor is running in Thumb mode.
Two EFCs are embedded in the SAM7S512 to control each bank of 256 Kbytes. Dual plane
organization allows concurrent Read and Program. Read from one memory plane may be per-
formed even while program or erase functions are being executed in the other memory plane.
One EFC is embedded in the SAM7S256/128/64/32/321/161/16 to control the single plane
256/128/64/32/16 Kbytes.