參數(shù)資料
型號(hào): AT91SAM7A3-AU
廠商: Atmel
文件頁(yè)數(shù): 4/39頁(yè)
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 256K 100LQFP
產(chǎn)品培訓(xùn)模塊: SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AT91SAM
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: CAN,I²C,MMC,SPI,SSC,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 62
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤(pán)
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7A3-EK-ND - KIT EVAL FOR AT91SAM7A3
12
6042DS–ATARM–14-Dec-06
AT91SAM7A3
6.
I/O Lines Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5V-tolerant, TDI is not. TMS,
TDI and TCK do not integrate any resistors and have to be pulled-up externally.
TDO is an output, driven at up to VDD3V3.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level.
The JTAGSEL pin integrates a permanent pull-down resistor so that it can be left unconnected
for normal operations.
6.2
Test Pin
The TST pin is used for manufacturing tests and integrates a pull-down resistor so that it can be
left unconnected for normal operations. Driving this line at a high level leads to unpredictable
results.
6.3
Reset Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. There is no constraint on the length of the reset pulse, and the reset controller
can guarantee a minimum pulse length. This allows connection of a simple push-button on the
NRST pin as system user reset, and the use of the NRST signal to reset all the components of
the system.
6.4
PIO Controller A and B Lines
All the I/O lines PA0 to PA31 and PB0 to PB29 are 5V-tolerant and all integrate a programmable
pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line
through the PIO Controllers.
5V-tolerant means that the I/O lines can drive voltage level according to VDD3V3, but can be
driven with a voltage at up to 5.5V. However, driving an I/O line with a voltage over VDD3V3
while the programmable pull-up resistor is enabled creates a current path through the pull-up
resistor from the I/O line to VDDIO. Care should be taken, especially at reset, as all the I/O lines
default as inputs with pull-up resistor enabled at reset.
6.5
Shutdown Logic Pins
The SHDW pin is an open drain output. It can be tied to VDDBU with an external pull-up resistor.
The FWUP, WKUP0 and WKUP1 pins are input-only. They can accept voltages only between
0V and VDDBU. It is recommended to tie these pins either to GND or to VDDBU with an external
resistor.
6.6
I/O Line Drive Levels
All the I/O lines can draw up to 2 mA.
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