參數(shù)資料
型號: AT91SAM7A3-AU
廠商: Atmel
文件頁數(shù): 2/39頁
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 256K 100LQFP
產(chǎn)品培訓(xùn)模塊: SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
標準包裝: 90
系列: AT91SAM
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: CAN,I²C,MMC,SPI,SSC,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7A3-EK-ND - KIT EVAL FOR AT91SAM7A3
10
6042DS–ATARM–14-Dec-06
AT91SAM7A3
5.
Power Considerations
5.1
Power Supplies
The AT91SAM7A3 has five types of power supply pins:
VDD3V3 pins. They power the voltage regulator, the I/O lines, the Flash and the USB
transceivers; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
VDD1V8 pins. They are the outputs of the 1.8V voltage regulator and they power the logic of
the device.
VDDPLL pin. It powers the PLL; voltage ranges from 1.65V to 1.95V, 1.8V typical. They can
be connected to the VDD1V8 pin with decoupling capacitor.
VDDBU pin. It powers the Slow Clock oscillator and the Real Time Clock, as well as a part of
the System Controller; ranges from 3.0V and 3.6V, 3.3V nominal.
VDDANA pin. It powers the ADC; ranges from 3.0V and 3.6V, 3.3V nominal.
No separate ground pins are provided for the different power supplies. Only GND pins are pro-
vided and should be connected as shortly as possible to the system ground plane.
5.2
Voltage Regulator
The AT91SAM7A3 embeds a voltage regulator that consumes less than 120 A static current
and draws up to 130 mA of output current.
Adequate output supply decoupling is mandatory for VDD1V8 (pin 99)to reduce ripple and avoid
oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF
(or 1 nF) NPO capacitor must be connected between VDD1V8 and GND as close to the chip as
possible. One external 3.3 F (or 4.7 F) X7R capacitor must be connected between VDD1V8
and GND.
All other VDD1V8 pins must be externally connected and have a proper decoupling capacitor (at
least 100 nF).
Adequate input supply decoupling is mandatory for VDD3V3 (pin 100) in order to improve star-
tup stability and reduce source voltage drop. The input decoupling capacitor should be placed
close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 F
X7R.
All other VDD3V3 pins must be externally connected and have a proper decoupling capacitor (at
least 100 nF).
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