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| 型號： | AT90S2313-10PC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 71/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 2K FLSH 10MHZ UART 20DIP |
| 標準包裝： | 18 |
| 系列： | AVR® 90S |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 10MHz |
| 連通性： | SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 15 |
| 程序存儲器容量： | 2KB（1K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
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1997 Microchip Technology Inc.
DS30234D-page 73
PIC16C6X
8.3
Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and gener-
ate an interrupt on overow which will wake the proces-
sor. However, special precautions in software are
needed to read-from or write-to the Timer1 register
pair, TMR1L and TMR1H (Section 8.3.2).
In asynchronous counter mode, Timer1 cannot be used
as a time-base for capture or compare operations.
8.3.1
EXTERNAL CLOCK INPUT TIMING WITH
UNSYNCHRONIZED CLOCK
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high time and low time requirements,
as specied in timing parameters (45 - 47).
8.3.2
READING AND WRITING TMR1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an unpre-
dictable value in the timer register.
Reading
the
16-bit
value
requires
some
care.
Example 8-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
EXAMPLE 8-1:
READING A 16-BIT
FREE-RUNNING TIMER
;
All Interrupts are disabled
MOVF
TMR1H,
W
;Read high byte
MOVWF
TMPH
;
MOVF
TMR1L,
W
;Read low byte
MOVWF
TMPL
;
MOVF
TMR1H,
W
;Read high byte
SUBWF
TMPH,
W
;Sub 1st read
;with 2nd read
BTFSC
STATUS,Z
;is result = 0
GOTO
CONTINUE
;Good 16-bit read
; TMR1L may have rolled over between the read
; of the high and low bytes. Reading the high
; and low bytes now will read a good value.
MOVF
TMR1H,
W
;Read high byte
MOVWF
TMPH
;
MOVF
TMR1L,
W
;Read low byte
MOVWF
TMPL
;
Re-enable Interrupt (if required)
CONTINUE
;Continue with
:
;your code
8.4
Timer1 Oscillator
A crystal oscillator circuit is built in-between pins T1OSI
(input) and T1OSO (amplier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 8-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must allow a software time delay to ensure
proper oscillator start-up.
TABLE 8-1:
CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Osc Type
Freq
C1
C2
LP
32 kHz
33 pF
100 kHz
15 pF
200 kHz
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz
Epson C-001R32.768K-A
± 20 PPM
100 kHz
Epson C-2 100.00 KC-P
± 20 PPM
200 kHz
STD XTL 200.000 kHz
± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
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