參數(shù)資料
型號: AT90S2313-10PC
廠商: Atmel
文件頁數(shù): 17/92頁
文件大?。?/td> 0K
描述: IC MCU 2K FLSH 10MHZ UART 20DIP
標(biāo)準(zhǔn)包裝: 18
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
24
AT90S2313
0839I–AVR–06/02
Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt
(at vector $003) is executed if a capture-triggering event occurs on PD6(ICP) (i.e., when
the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2313 and always reads as zero.
Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$006) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2313 and always read as zero.
Timer/Counter Interrupt FLAG
Register – TIFR
Bit 7 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
(T i m er/ C ounte r1 O v e rf l o w Int errupt En a b l e ) a n d T O V 1 a re s et (one), t he
Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 changes counting direction at $0000.
Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register1 A). OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Match Interrupt Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare Match Interrupt is executed.
Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and always read as zero.
Bit 3 – ICF1: Input Capture Flag 1
T h e ICF 1 bi t is se t (on e) to fla g a n i np ut ca ptu re e ven t, in di cati ng that th e
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
Bit
7
6
5
4
3
2
1
0
$38 ($58)
TOV1
OCF1A
ICF1
TOV0
TIFR
Read/Write
R/W
R
R/W
R
R/W
R
Initial value
0
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