參數(shù)資料
型號: AT90PWM1-16SU
廠商: Atmel
文件頁數(shù): 74/90頁
文件大小: 0K
描述: MCU AVR 8K FLASH 16MHZ 24-SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1,116
系列: AVR® 90PWM 照明
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 19
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: ATSTK600-RC19-ND - STK600 ROUTING CARD AVR
ATSTK600-SOIC-ND - STK600 SOCKET/ADAPTER FOR SOIC
76
4378C–AVR–09/08
AT90PWM1
13. Timer/Counter0 and Timer/Counter1 Prescalers
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counter1 and
Timer/Counter0.
13.0.1
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
CLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either f
CLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or
f
CLK_I/O/1024.
13.0.2
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
13.0.3
External Clock Source
An external clock source applied to the Tn/T0 pin can be used as Timer/Counter clock
(clk
T1/clkT0). The Tn/T0 pin is sampled once every system clock cycle by the pin synchronization
logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1
shows a functional equivalent block diagram of the Tn/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (clk
I/O). The latch
is transparent in the high period of the internal system clock.
The edge detector generates one clk
T1/clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 13-1. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Tn_sync
(To Clock
Select Logic)
Edge Detector
Synchronization
DQ
LE
DQ
Tn
clk
I/O
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