參數(shù)資料
型號: AT89LP428-20PU
廠商: Atmel
文件頁數(shù): 66/149頁
文件大?。?/td> 0K
描述: MCU 8051 4K FLASH SPI 28PDIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 14
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
23
3654A–MICRO–8/09
AT89LP428/828
7.
Reset
During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the
program starts execution from the Reset Vector, 0000H. The AT89LP428/828 has five sources
of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset.
7.1
Power-on Reset
A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level V
POR
is nominally 1.4V. The POR is activated whenever V
CC is below the detection level. The POR cir-
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on. A
power-on sequence is shown in Figure 7-1 on page 24. When V
CC reaches the Power-on Reset
threshold voltage V
POR, an initialization sequence lasting tPOR is started. When the initialization
sequence completes, the start-up timer determines how long the device is kept in POR after V
CC
rise. The POR signal is activated again, without any delay, when V
CC falls below the POR
threshold level. A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. The internally
generated reset can be extended beyond the power-on period by holding the RST pin low longer
than the time-out.
Table 6-2.
CLKREG
– Clock Control Register
CLKREG = 8FH
Reset Value = 0000 0000B
Not Bit Addressable
TPS3TPS2TPS1TPS0
CDV2
CDV1
CDV0
COE
Bit
7
6
543
21
0
Symbol
Function
TPS [3 - 0]
Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2 and the Watchdog Timer.
The prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the
value stored in the TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock
cycle (TPS = 0000B). To configure the timers to count at a standard 8051 rate of once every 12 clock cycles, TPS
should be set to 1011B.
CDV [2 - 0]
System Clock Division. Determines the frequency of the system clock relative to the oscillator clock source.
CDIV2
CDIV1
CDIV0
System Clock Frequency
00
0
fOSC/1
00
1
fOSC/2
01
0
f
OSC/4
01
1
fOSC/8
10
0
fOSC/16
10
1
f
OSC/32
11
0
reserved
11
1
reserved
COE
Clock Out Enable. Set COE to output the system clock divided by 2 on XTAL2 (P4.1). The internal RC oscillator or
external clock source must be selected in order to use this feature and P4.1 must be configured as an output.
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