參數(shù)資料
型號(hào): AT89C51SND1C-7HTUL
廠商: Atmel
文件頁(yè)數(shù): 7/42頁(yè)
文件大?。?/td> 0K
描述: IC MCU 64KB FLASH MEM 81-CBGA
標(biāo)準(zhǔn)包裝: 250
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 44
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-CBGA
包裝: 托盤(pán)
15
4109LS–8051–02/08
AT8xC51SND1C
6.
Peripherals
The AT8xC51SND1C peripherals are briefly described in the following sections. For further
details on how to interface (hardware and software) to these peripherals, please refer to the
AT8xC51SND1C design guide.
6.1
Clock Generator System
The AT8xC51SND1C internal clocks are extracted from an on-chip PLL fed by an on-chip oscil-
lator. Four clocks are generated respectively for the C51 core, the MP3 decoder, the audio
interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscilla-
tor clock. The MP3 decoder clock is generated by dividing the PLL output clock. The audio
interface sample rates are also obtained by dividing the PLL output clock.
6.2
Ports
The AT8xC51SND1C implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition
to performing general-purpose I/O, some ports are capable of external data memory operations;
others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an
output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate
external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose
I/O and alternate functions.
6.3
Timers/Counters
The AT8xC51SND1C implements the two general-purpose, 16-bit Timers/Counters of a stan-
dard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to
operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a
Timer/Counter runs for a programmed length of time, then issues an interrupt request. When
operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a
preset number of counts, the Counter issues an interrupt request.
6.4
Watchdog Timer
The AT8xC51SND1C implements a hardware Watchdog Timer that automatically resets the
chip if it is allowed to time out. The WDT provides a means of recovering from routines that do
not complete successfully due to software or hardware malfunctions.
6.5
MP3 Decoder
The AT8xC51SND1C implements a MPEG I/II audio layer 3 decoder (known as MP3 decoder).
In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three
sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3 allows highest com-
pression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of
CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32 MBytes of storage, can be
encoded into only 2.7 MBytes of MPEG I audio layer 3 data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 KHz are
supported for low bit rates applications.
The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data into a
PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
Additional features are supported by the AT8xC51SND1C MP3 decoder such as volume, bass,
medium, and treble controls, bass boost effect and ancillary data extraction.
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