參數(shù)資料
型號: AT89C51SND1C-7HTUL
廠商: Atmel
文件頁數(shù): 30/42頁
文件大?。?/td> 0K
描述: IC MCU 64KB FLASH MEM 81-CBGA
標準包裝: 250
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 44
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
數(shù)據(jù)轉換器: A/D 2x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-CBGA
包裝: 托盤
36
4109LS–8051–02/08
AT8xC51SND1C
7.4.4
Analog to Digital Converter
7.4.4.1
Definition of symbols
Table 39. Analog to Digital Converter Timing Symbol Definitions
7.4.4.2
Characteristics
Table 40. Analog to Digital Converter AC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Notes:
1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code.
2. The differential non-linearity is the difference between the actual step width and the ideal step
width (see Figure 7-22).
3. The integral non-linearity is the peak difference between the center of the actual step and the
ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 7-22).
4. The offset error is the absolute difference between the straight line which fits the actual trans-
fer curve (after removing of gain error), and the straight line which fits the ideal transfer curve
5. The gain error is the relative difference in percent between the straight line which fits the actual
transfer curve (after removing of offset error), and the straight line which fits the ideal transfer
curve (see Figure 7-22).
Signals
Conditions
C
Clock
H
High
E
Enable (ADEN bit)
L
Low
S
Start Conversion
(ADSST bit)
Symbol
Parameter
Min
Max
Unit
T
CLCL
Clock Period
4
s
T
EHSH
Start-up Time
4
s
T
SHSL
Conversion Time
11T
CLCL
s
DLe
Differential non-
linearity error(1)(2)
1
LSB
ILe
Integral non-
linearity errorss(1)(3)
2
LSB
OSe
Offset error(1)(4)
4
LSB
Ge
Gain error(1)(5)
4
LSB
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