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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AT89C51RB2-3CSIM |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 11/127闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC 8051 MCU FLASH 16K 40DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 9 |
| 绯诲垪锛� | 89C |
| 鏍稿績铏曠悊鍣細 | 8051 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 60MHz |
| 閫ｉ€氭€э細 | SPI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 32 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 16KB锛�16K x 8锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 1.25K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 40-DIP锛�0.600"锛�15.24mm锛� |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | AT89STK-11-ND - KIT STARTER FOR AT89C51RX2 |
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108
AT89C51RB2/RC2
4180E鈥�8051鈥�10/06
Notes:
1. Operating I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 49.), VIL =
VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
46).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = V
3. Power Down I
CC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi V
OL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Icc Flash Write operation current while an on-chip flash page write is on going.
9. Flash Retention is guaranteed with the same formula for V
CC Min down to 0.
V
OH1
Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
VCC = 5V 卤 10%
IOH = -200 渭A
IOH = -3.2 mA
IOH = -7.0 mA
0.9 VCC
V
VCC = 2.7V to 5.5V
IOH = -10 渭A
RRST
RST Pulldown Resistor
50
200(5)
250
k
惟
IIL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
渭AV
IN = 0.45V
ILI
Input Leakage Current for P0 only
卤10
渭A
0.45V < VIN < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
-650
渭AV
IN = 2.0V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 3 MHz
TA = 25
掳C
IPD
Power Down Current
100
150
渭A4.5V < V
CC < 5.5V
(3)
ICCOP
Power Supply Current on normal mode
0.4 x Frequency (MHz) + 5
mA
VCC = 5.5V
(1)
ICCIDLE
Power Supply Current on idle mode
0.3 x Frequency (MHz) + 5
mA
VCC = 5.5V
(1)
I
CCProg
Power Supply Current during flash Write / Erase
0.4 x
Frequency
(MHz) + 20
mA
V
CC = 5.5V
(8)
TA = -40掳C to +85掳C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
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