參數(shù)資料
型號： AT89C51CC01UA-SLSUM
廠商： Atmel
文件頁數(shù)： 41/123頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 972
系列： AT89C CAN
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 托盤
配用： AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
其它名稱： AT89C51CC01UASLSUM
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 133
dsPIC33F
6.4
Interrupt Setup Procedures
6.4.1
INITIALIZATION
To configure an interrupt source:
1.
Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
2.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
3.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
4.
Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
6.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., C or assembler) and
the language development toolsuite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of interrupt that the ISR handles. Otherwise, the
ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
6.4.3
TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
6.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using the following
procedure:
1.
Push the current SR value onto the software
stack using the PUSH instruction.
2.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (level 8-level 15)
cannot be disabled.
The DISI instruction provides a convenient way to dis-
able interrupts of priority levels 1-6 for a fixed period of
time. Level 7 interrupt sources are not disabled by the
DISI
instruction.
Note:
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to priority level 4.
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參數(shù)描述
AT89C51CC01UU-RLTUM 功能描述:8位微控制器 -MCU Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C51CC01UU-SLSUM 功能描述:8位微控制器 -MCU Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C51CC02 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash
AT89C51CC02CA-RATUM 功能描述:8位微控制器 -MCU CAN/C51 Boot CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C51CC02CA-SISIM 制造商:Atmel Corporation 功能描述:
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