參數(shù)資料
型號: AT89C51CC01UA-SLSUM
廠商: Atmel
文件頁數(shù): 31/123頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 972
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 托盤
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
其它名稱: AT89C51CC01UASLSUM
PIC18F2XK20/4XK20
DS41303G-page 126
2010 Microchip Technology Inc.
TABLE 10-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB6/KBI2/PGC
RB6
0
O
DIG
LATB<6> data output.
1
I
TTL
PORTB<6> data input; Programmable weak pull-up.
KBI2
1
I
TTL
Interrupt-on-pin change.
PGC
x
I
ST
Serial execution (ICSP) clock input for ICSP and ICD operation.(3)
RB7/KBI3/PGD
RB7
0
O
DIG
LATB<7> data output.
1
I
TTL
PORTB<7> data input; Programmable weak pull-up.
KBI3
1
I
TTL
Interrupt-on-pin change.
PGD
x
O
DIG
Serial execution data output for ICSP and ICD operation.(3)
x
I
ST
Serial execution data input for ICSP and ICD operation.(3)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
LATB
PORTB Data Latch Register (Read and Write to Data Latch)
TRISB
PORTB Data Direction Control Register
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
SLRCON
SLRE(1)
SLRD(1)
SLRC
SLRB
SLRA
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
RBPU
INTEDG0
INTEDG1 INTEDG2
TMR0IP
—RBIP
INTCON3
INT2IP
INT1IP
—INT2IE
INT1IE
INT2IF
INT1IF
ANSELH
ANS12
ANS11
ANS10
ANS9
ANS8
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1:
Not implemented on PIC18F2XK20 devices.
TABLE 10-3:
PORTB I/O SUMMARY (CONTINUED)
Pin
Function
TRIS
Setting
I/O
Type
Description
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note
1:
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
2:
Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
3:
All other pin functions are disabled when ICSP or ICD are enabled.
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