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參數(shù)資料
| 型號(hào)： | AT89C51AC2-SLSUM |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 67/121頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 32K 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction |
| 標(biāo)準(zhǔn)包裝： | 972 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 1.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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5
A/T89C51AC2
4127H–8051–02/08
P3.0:7
I/O
Port 3:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal
pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a
source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.
The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for
TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:
P3.0/RxD:
Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
P3.1/TxD:
Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface
P3.2/INT0:
External interrupt 0 input/timer 0 gate control input
P3.3/INT1:
External interrupt 1 input/timer 1 gate control input
P3.4/T0:
Timer 0 counter input
P3.5/T1:
Timer 1 counter input
P3.6/WR:
External Data Memory write strobe; latches the data byte from port 0 into the external data memory
P3.7/RD:
External Data Memory read strobe; Enables the external data memory.
It can drive CMOS inputs without external pull-ups.
P4.0:1
I/O
Port 4:
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal
pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of
current (IIL, on the datasheet) because of the internal pull-up transistor.
P4.0
P4.1:
It can drive CMOS inputs without external pull-ups.
RESET
I/O
Reset:
A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down
resistor to VSS permits power-on reset using only an external capacitor to VCC.
ALE
O
ALE:
An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is
activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are
executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.
PSEN
O
PSEN:
The Program Store Enable output is a control signal that enables the external program memory of the bus during external
fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when
executing from of the external program memory two activations of PSEN are skipped during each access to the external Data
memory. The PSEN is not activated for internal fetches.
EA
I
EA:
When External Access is held at the high level, instructions are fetched from the internal Flash when the program counter is
less then 8000H. When held at the low level,A/T89C51AC2 fetches all instructions from the external program memory
.
XTAL1
I
XTAL1:
Input of the inverting oscillator amplifier and input of the internal clock generator circuits.
To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate
above a frequency of 16 MHz, a duty cycle of 50% should be maintained.
XTAL2
O
XTAL2:
Output from the inverting oscillator amplifier.
Table 1. Pin Description (Continued)
Pin Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B2H-IY-F1 | CONVERTER MOD DC/DC 52V 50W |
| VJ2225A561JBEAT4X | CAP CER 560PF 500V 5% NP0 2225 |
| VI-B24-IY-F4 | CONVERTER MOD DC/DC 48V 50W |
| VJ2225A561JBLAT4X | CAP CER 560PF 630V 5% NP0 2225 |
| VI-J1Y-IY-F1 | CONVERTER MOD DC/DC 3.3V 33W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT89C51AC3 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with 64KB Flash Memory |
| AT89C51AC3_04 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Microcontrollers |
| AT89C51AC3_05 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with 64KB Flash Memory |
| AT89C51AC3_08 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with 64KB Flash Memory |
| AT89C51AC3-RDTIM | 功能描述:IC 8051 MCU FLASH 64K 64VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 標(biāo)準(zhǔn)包裝:1,500 系列:AVR® ATtiny 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，LIN，SPI，UART/USART，USI 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:8KB（4K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 11x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:帶卷 (TR) |
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