參數(shù)資料
型號： AT89C51AC2-SLSUM
廠商： Atmel
文件頁數(shù)： 32/121頁
文件大小： 0K
描述： IC 8051 MCU FLASH 32K 44PLCC
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 972
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
18
A/T89C51AC2
4127H–8051–02/08
Power Management
Two power reduction modes are implemented in the A/T89C51AC2: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 Mode detailed in Section “Clock”.
Reset Pin
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a
high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of
the internal registers like SFRs, PC, etc. and to unpredictable behavior of the microcon-
troller. A warm reset can be applied either directly on the RST pin or indirectly by an
internal reset source such as a watchdog, PCA, timer, etc.
At Power-up (Cold Reset) Two conditions are required before enabling a CPU start-up:
VDD must reach the specified VDD range,
The level on xtal1 input must be outside the specification (VIH, VIL).
If one of these two conditions are not met, the microcontroller does not start correctly
and can execute an instruction fetch from anywhere in the program space. An active
level applied on the RST pin must be maintained until both of the above conditions are
met. A reset is active when the level VIH1 is reached and when the pulse width covers
the period of time where VDD and the oscillator are not stabilized. Two parameters have
to be taken into account to determine the reset pulse width:
VDD rise time (vddrst),
Oscillator startup time (oscrst).
To determine the capacitor the highest value of these two parameters has to be chosen.
The reset circuitry is shown in Figure 7.
Figure 7. Reset Circuitry
Table 13 and Table 15 give some typical examples for three values of VDD rise times,
two values of oscillator start-up time and two pull-down resistor values.
Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor
Note:
These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply de coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
oscrst/vddrst
1ms
10ms
100ms
5 ms
2.7 F
4.7 F
47 F
20 ms
10 F
15 F
47 F
0
VDD
Rrst
Crst
RST pin
Internal reset
Reset input circuitry
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