參數(shù)資料
型號： AT89C5131A-PUTIM
廠商： Atmel
文件頁數(shù)： 48/176頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K USB 32QFN
標(biāo)準(zhǔn)包裝： 260
系列： AT89C513x
核心處理器： C52X2
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設(shè)備： LED，POR，PWM，WDT
輸入/輸出數(shù)： 18
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤
包裝： 托盤
配用： AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
139
AT89C5131
4136C–USB–04/05
Reset Value = 00h
Table 96. UEPSTAX (S:CEh) USB Endpoint X Status Register
76
54
32
10
DIR
RXOUTB1
STALLRQ
TXRDY
STL/CRC
RXSETUP
RXOUTB0
TXCMP
Bit Number
Bit
Mnemonic
Description
7DIR
Control Endpoint Direction
This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h)
This bit determines the Control data and status direction.
The device firmware will set this bit ONLY for the IN data stage, before any other USB operation. Otherwise, the device
firmware will clear this bit.
6
RXOUTB1
Received OUT Data Bank 1 for Endpoints 4, 5 and 6 (Ping-pong mode)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 (only in Ping-pong mode).
Then, the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint
Interrupt Register” on page 143) and all the following OUT packets to the endpoint bank 1 are rejected (NAK’ed) until this
bit has been cleared, excepted for Isochronous Endpoints.
This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
5STALLRQ
Stall Handshake Request
Set this bit to request a STALL answer to the host for the next handshake.Clear this bit otherwise.
For CONTROL endpoints: cleared by hardware when a valid SETUP PID is received.
4TXRDY
TX Packet Ready
Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data will be written into the
endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero
Length Packet.
This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has
acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is
3
STLCRC
Stall Sent/CRC error flag
- For Control, Bulk and Interrupt Endpoints:
This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint
It will be cleared by the device firmware.
- For Isochronous Endpoints (Read-Only):
This bit is set by hardware if the last received data is corrupted (CRC error on data).
This bit is updated by hardware when a new data is received.
2
RXSETUP
Received SETUP
This bit is set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the
register are cleared by hardware and the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h
It will be cleared by the device firmware after reading the SETUP data from the endpoint FIFO.
1
RXOUTB0
Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint
page 143) and all the following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this bit has been cleared,
excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the
content of the endpoint FIFO, even if its Data packet is received while this bit is set.
This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
0TXCMPL
Transmitted IN Data Complete
This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been
accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if
This bit will be cleared by the device firmware before setting TXRDY.
相關(guān)PDF資料
PDF描述
AT89C5131A-TISIL IC 8051 MCU FLASH 32K USB 28SOIC
AT89C5132-RORUL MCU 8051 FLASH USB 80TQFP
AT89C51AC3-SLSIM IC 8051 MCU FLASH 64K 44PLCC
AT89C51CC03C-RLRIM IC 8051 MCU FLASH 64K 44VQFP
AT89C51ED2-SMRUM IC MCU FLASH 8051 64K 5V 68PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT89C5131A-PUTUM 功能描述:8位微控制器 -MCU C5130A 32K Flash USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89C5131A-RDTIL 功能描述:IC 8051 MCU FLASH 32K USB 64VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT89C513x 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件
AT89C5131A-RDTIM 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with Full Speed USB Device
AT89C5131A-RDTUL 功能描述:8位微控制器 -MCU 32K Flash 3V USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89C5131A-RDTUM 功能描述:8位微控制器 -MCU C5130A 32K Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*