參數(shù)資料
型號(hào): AT89C5115-TISUM
廠商: Atmel
文件頁數(shù): 89/113頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 28SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 972
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.400",10.16mm 寬)
包裝: 管件
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
2007-2011 Microchip Technology Inc.
DS70265E-page 77
dsPIC33FJ12MC201/202
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
U-0
R/W-0
U-0
SFTACERR
DIV0ERR
MATHERR
ADDRERR
STKERR
OSCFAIL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
NSTDIS:
Interrupt Nesting Disable bit
1
= Interrupt nesting is disabled
0
= Interrupt nesting is enabled
bit 14
OVAERR:
Accumulator A Overflow Trap Flag bit
1
= Trap was caused by overflow of Accumulator A
0
= Trap was not caused by overflow of Accumulator A
bit 13
OVBERR:
Accumulator B Overflow Trap Flag bit
1
= Trap was caused by overflow of Accumulator B
0
= Trap was not caused by overflow of Accumulator B
bit 12
COVAERR:
Accumulator A Catastrophic Overflow Trap Flag bit
1
= Trap was caused by catastrophic overflow of Accumulator A
0
= Trap was not caused by catastrophic overflow of Accumulator A
bit 11
COVBERR:
Accumulator B Catastrophic Overflow Trap Flag bit
1
= Trap was caused by catastrophic overflow of Accumulator B
0
= Trap was not caused by catastrophic overflow of Accumulator B
bit 10
OVATE:
Accumulator A Overflow Trap Enable bit
1
= Trap overflow of Accumulator A
0
= Trap disabled
bit 9
OVBTE:
Accumulator B Overflow Trap Enable bit
1
= Trap overflow of Accumulator B
0
= Trap disabled
bit 8
COVTE:
Catastrophic Overflow Trap Enable bit
1
= Trap on catastrophic overflow of Accumulator A or B enabled
0
= Trap disabled
bit 7
SFTACERR:
Shift Accumulator Error Status bit
1
= Math error trap was caused by an invalid accumulator shift
0
= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR:
Arithmetic Error Status bit
1
= Math error trap was caused by a divide by zero
0
= Math error trap was not caused by a divide by zero
bit 5
Unimplemented:
Read as ‘0’
bit 4
MATHERR:
Arithmetic Error Status bit
1
= Math error trap has occurred
0
= Math error trap has not occurred
bit 3
ADDRERR:
Address Error Trap Status bit
1
= Address error trap has occurred
0
= Address error trap has not occurred
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