參數(shù)資料
型號： AT89C5115-TISUM
廠商： Atmel
文件頁數(shù)： 42/113頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 16K 28SOIC
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 972
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
EEPROM 大小： 2K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.400"，10.16mm 寬）
包裝： 管件
配用： AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
34
AT89C5115
4128G–8051–02/08
Overview of FM0
Operations
The CPU interfaces the Flash memory through the FCON register and AUXR1 register.
These registers are used to:
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the Flash memory (busy/not busy)
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting FPS bit takes precedence on the EEE bit in EECON register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 21. A MOVC instruction is then used for reading these spaces.
Table 21. FM0 blocks Select bits
Launching Programming
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 22 summarizes the memory
spaces to program according to FMOD1:0 bits.
Table 22. Programming Spaces
Note:
The sequence 5xh and Axh must be executing without instructions between them other-
wise the programming is aborted.
Interrupts that may occur during programming time must be disabled to avoid any spuri-
ous exit of the programming mode.
FMOD1
FMOD0
FM0 Adressable Space
0
User (0000h-3FFFh)
0
1
Extra Row(FF80h-FFFFh)
1
0
Hardware Security Byte (0000h)
1
Reserved
Write to FCON
Operation
FPL3:0
FPS
FMOD1
FMOD0
User
5
x
0
No action
A
x
0
Write the column latches in user
space
Extra Row
5
x
0
1
No action
A
x
0
1
Write the column latches in extra row
space
Hardware
Security
Byte
5
x
1
0
No action
A
x
1
0
Write the fuse bits space
Reserved
5
x
1
No action
A
x
1
No action
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