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參數(shù)資料
| 型號： | AT88RF256-12 |
| 廠商： | Atmel Corp. |
| 英文描述： | 125 kHz RFID Chip for Cards and Tags |
| 中文描述： | 125千赫RFID芯片的卡和標簽 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 190K |
| 代理商： | AT88RF256-12 |
AT88RF256-12
7
Option Page
Bits are listed below in the order in which they must be sent
to the chip when the
“
Write Lock Byte
”
or
“
Write
Configuration Bits
”
command is sent to the chip. The
“
Default
”
column lists the values that will be in the die upon
shipment from Atmel.
When reading this page, all 32 bits are read in this order.
This page cannot be written with a single 32-bit command.
The
“
Write Lock Byte
”
command is used for the first byte
only, and the
“
Write Configuration Bits
”
command is used
for the last three bytes.
The
“
Default
”
column reflects the default value that the
options have upon shipment from the Atmel factory.
Lock Byte
Configuration Bits
Name
#
Default
Description
LOCK[7:0]
8
0x80
If 1, locks the corresponding user page against further writes. Page 7 contains the serial
number and is locked on shipment from the factory.
Name
#
Default
Description
PU_LEN[3:0]
4
0
Number of ID bytes after first 4. Total ID size range: 4 - 19 bytes.
STRT_STOP
1
1
Start Stop bit enable. If 1 both start and stop bits will be sent, the default.
STOP_1
1
1
Value of stop bit, start bit is opposite value. Default is stop = 1, start = 0.
RANDOM[1:0]
2
00
Frames (ID + 8 transmit bit time listening window) between ID transmissions:
00 Continuous frames
01 Random null frames, mean number = 8
10 Random null frames, mean number = 32
11 Random null frames, mean number = 128
TST_EN
1
0
Test mode, leave at 0.
PW_ON
1
0
Password enable, if 1 password is page 9 of EEPROM.
TCLK_GEN[5:0]
6
0
Transmit range of 16 clocks/bit to 1024 clocks/bit: (value+1)*16 = # clocks/bit. Default is
16 clocks per bit.
RCLK_GEN
1
1
Receive range of 32 clocks/bit to 4096 clocks/bit. Default is 64 clocks per bit.
0 = (tclk clocks/bit)*2
1 = (tclk clocks/bit)*4
ENCODE[1:0]
2
10
First stage encoding scheme for transmission. Default is Miller.
00 = No encoding (NRZ)
01 = Manchester
10 = Miller
11 = None (NRZ)
INV_ENC
1
0
Output of encoder is inverted before input to modulator.
MODULATE[1:0]
2
00
Modulator control scheme for transmission. Default is AM.
00 = No special modulation (AM / ASK)
01 = PSK1, phase shift on every logic 1, sampled at beginning of bit time.
10 = PSK2, phase shift on every state change at beginning or middle of bit.
11 = Subcarrier gating of 62.5 kHz clock
PW_LOCK
1
0
Locks the password page against further writes.
CONFIG_LOCK
1
0
Locks the configuration page (but not LOCK[7:0] against further writes).
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