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參數(shù)資料
| 型號(hào)： | AT85C51SND3B1-7FTUL |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 101/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DECODER/ENCODER DGTL 100CBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 音頻編碼器/解碼器 |
| 應(yīng)用： | 移動(dòng)電話，手機(jī)，視頻顯示器 |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CTBGA（9x9） |
| 包裝： | 托盤 |
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82
AT85C51SND3B
7632D–MP3–01/07
Registers
Reset Value = 0000 0000b
Table 94. DFCON Register
DFCON (1.89h) – DFC Control Register
7
6
5
4
3
2
1
0
-
DFRES
-
DFCRCEN
DFPRIO1
DFPRIO0
DFABTM
DFEN
Bit
Number
Bit
Mnemonic Description
5
-
Reserved
The value read from this bit is always 0. Do not set this bit.
6
DFRES
Data Flow Controller Reset Bit
Set then clear this bit to reset the Data Flow Controller by software.
5
-
Reserved
The value read from this bit is always 0. Do not set this bit.
4
DFCRCEN
CRC Enable Bit
Set to enable CRC calculation on channel 0.
Clear to disable CRC calculation.
3-2
DFPRIO1:0
Data Flow Channel Priority Assignment Bits
Refer to Table 93 for channel priority assignment description.
1
DFABTM
Data Flow Abort Mode Bit
Set to trigger a delayed abort.
Clear to trigger an immediate abort.
0
DFEN
Data Flow Controller Enable Bit
Set to enable the Data Flow Controller.
Clear to disable the Data Flow Controller.
Table 95. DFCSTA Register
DFCSTA (1.88h Bit Addressable) – DFC Channel Status Register
7
6
5
4
3
2
1
0
DRDY1
SRDY1
EOFI1
DFBSY1
DRDY0
SRDY0
EOFI0
DFBSY0
Bit
Number
Bit
Mnemonic Description
7
DRDY1
Channel 1 Destination Ready Flag
Set by hardware when the destination peripheral of channel 1 is ready.
Cleared by hardware when the destination peripheral of channel 1 is not ready.
6
SRDY1
Channel 1 Source Ready Flag
Set by hardware when the source peripheral of channel 1 is ready.
Cleared by hardware when the source peripheral of channel 1 is not ready.
5
EOFI1
Channel 1 End Of Data Flow Interrupt Flag
Set by hardware at the end of a channel 1 data flow transfer.
Cleared by software by setting EOFIA1 in DFCCON. Can not be set by software.
4
DFBSY1
Channel 1 Busy Flag
Set by hardware when a transfer is on-going on channel 1.
Cleared by hardware when no transfer is on-going on channel 1.
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| AT85C51SND3B1N-DDV | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B1N-RTTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B1-RTTUL | 功能描述:音頻 DSP MP3/WMA USB2.0 w/o DAC+DC/DC RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B2-RTTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3BX | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:MP3 Microcontrollers |
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