參數(shù)資料
型號: AT32UC3L032-ZAUT
廠商: Atmel
文件頁數(shù): 100/174頁
文件大?。?/td> 0K
描述: IC MCU 32K FLASH 16K 48-VQFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
AVR® UC3 Introduction
標準包裝: 2,080
系列: AVR®32 UC3 L
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 托盤
其它名稱: 32UC3L032-ZAUT
32UC3L032-ZAUT-ND
2011-2012 Microchip Technology Inc.
Preliminary
DS70657E-page 491
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
APPENDIX A: REVISION HISTORY
Revision A (April 2011)
This is the initial released version of the document.
Revision B (July 2011)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in Table A-1.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-bit
Digital Signal Controllers
and Microcontrollers”
Changed all pin diagrams references of VLAP to TLA.
Section 4.0 “Memory
Organization”
Updated the All Resets values for CLKDIV and PLLFBD in the System Control
Register Map (see Table 4-35).
Section 5.0 “Flash Program
Memory”
Updated “one word” to “two words” in the first paragraph of Section 5.2 “RTSP
Operation”.
Section 9.0 “Oscillator
Configuration”
Updated the PLL Block Diagram (see Figure 9-2).
Updated the Oscillator Mode, Fast RC Oscillator (FRC) with divide-by-N and PLL
(FRCPLL), by changing (FRCDIVN + PLL) to (FRCPLL).
Changed (FRCDIVN + PLL) to (FRCPLL) for COSC<2:0> = 001 and
NOSC<2:0> = 001 in the Oscillator Control Register (see Register 9-1).
Changed the POR value from 0 to 1 for the DOZE<1:0> bits, from 1 to 0 for the
FRCDIV<0> bit, and from 0 to 1 for the PLLPOST<0> bit; Updated the default
definitions for the DOZE<2:0> and FRCDIV<2:0> bits and updated all bit definitions
for the PLLPOST<1:0> bits in the Clock Divisor Register (see Register 9-2).
Changed the POR value from 0 to 1 for the PLLDIV<5:4> bits and updated the default
definitions for all PLLDIV<8:0> bits in the PLL Feedback Division Register (see
Register 9-2).
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Updated the bit definitions for the IRNG<1:0> bits in the CTMU Current Control
Register (see Register 22-3).
Section 25.0 “Op amp/
Comparator Module”
Updated the voltage reference block diagrams (see Figure 25-1 and Figure 25-2).
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