- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3828 > AT32UC3A0512-ALTT (Atmel)MCU AVR32 512K FLASH 144LQFP PDF資料下載
參數(shù)資料
| 型號： | AT32UC3A0512-ALTT |
| 廠商： | Atmel |
| 文件頁數(shù)： | 90/97頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU AVR32 512K FLASH 144LQFP |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction AVR® UC3 Introduction |
| 標(biāo)準(zhǔn)包裝： | 300 |
| 系列： | AVR®32 UC3 A0 |
| 核心處理器： | AVR |
| 芯體尺寸： | 32-位 |
| 速度： | 66MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，SPI，SSC，UART/USART，USB OTG |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 109 |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
| 配用： | ATEVK1105-ND - KIT EVAL FOR AT32UC3A0 ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR ATEVK1100-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁當(dāng)前第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
2006 Microchip Technology Inc.
DS70119E-page 89
dsPIC30F6010
FIGURE 15-2:
EDGE-ALIGNED PWM
15.4
Center-Aligned PWM
Center-aligned PWM signals are produced by the mod-
ule when the PWM time base is configured in an
Up/Down Counting mode (see Figure 15-3).
The PWM compare output is driven to the active state
when the value of the duty cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is equal to
the value held in the PTPER register.
FIGURE 15-3:
CENTER-ALIGNED PWM
15.5
PWM Duty Cycle Comparison
Units
There are four 16-bit special function registers (PDC1,
PDC2, PDC3 and PDC4) used to specify duty cycle
values for the PWM module.
The value in each duty cycle register determines the
amount of time that the PWM output is in the active
state. The duty cycle registers are 16 bits wide. The
LSb of a duty cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
15.5.1
DUTY CYCLE REGISTER BUFFERS
The four PWM duty cycle registers are double-buffered
to allow glitchless updates of the PWM outputs. For
each duty cycle, there is a duty cycle register that is
accessible by the user and a second duty cycle register
that holds the actual compare value used in the present
PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER reg-
ister occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
duty cycle registers when the PWM time base is dis-
abled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
Period
Duty Cycle
0
PTPER
PTMR
Value
New Duty Cycle Latched
0
PTPER
PTMR
Value
Period
Period/2
Duty
Cycle
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT32UC3A0512-ALTR | MCU AVR32 512K FLASH 144LQFP |
| ATMEGA88PV-10PU | MCU AVR 8K ISP FLASH 10MHZ 28DIP |
| HM2R06P1 | MILLIPACS RCP HSG |
| ATMEGA88PV-10MU | MCU AVR 8K ISP FLASH 10MHZ 32QFN |
| ATMEGA88PV-10AU | MCU AVR 8K ISP FLSH 10MHZ 32TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT32UC3A0512-ALTTA | 功能描述:32位微控制器 - MCU UC3A0 512Kb flash -40/+85DEG AUTO RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| AT32UC3A0512-ALU | 制造商:Atmel Corporation 功能描述: |
| AT32UC3A0512-ALUR | 功能描述:32位微控制器 - MCU 512KB, 144LQFP 85deg. Green RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| AT32UC3A0512-ALUT | 功能描述:32位微控制器 - MCU 32-bit 512KB Flash RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| AT32UC3A0512AU-ALTRA | 功能描述:32位微控制器 - MCU 512K FlashAUD144LQFP -40/+85o AUTO T&R RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。