參數(shù)資料
型號: AT32AP7002-CTUR
廠商: Atmel
文件頁數(shù): 14/83頁
文件大?。?/td> 0K
描述: IC MCU AVR32 196-CBGA
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR®32 AP7
核心處理器: AVR
芯體尺寸: 32-位
速度: 150MHz
連通性: EBI/EMI,I²C,MMC,PS2,SPI,SSC,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: D/A 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 196-TFBGA,CSBGA
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AT32AP7002-CTURDKR
21
32054F–AVR32–09/09
AT32AP7002
6.2.7
Unimplemented instructions
The following instructions are unimplemented in AVR32 AP, and will cause an Unimplemented
Instruction Exception if executed:
mems
memc
memt
6.2.8
Exceptions and Interrupts
AVR32 AP incorporates a powerful exception handling scheme. The different exception
sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensur-
ing a well-defined behavior when multiple exceptions are received simultaneously. Additionally,
pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a
lower priority class. Each priority class has dedicated registers to keep the return address and
status register thereby removing the need to perform time-consuming memory operations to
save this information.
There are four levels of external interrupt requests, all executing in their own context. The INT3
context provides dedicated shadow registers ensuring low latency for these interrupts. An inter-
rupt controller does the priority handling of the external interrupts and provides the autovector
offset to the CPU.
The addresses and priority of simultaneous events are shown in Table 6-2 on page 22.
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