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參數(shù)資料
| 型號： | AT25F1024N-10SI-2.7 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Hex Buffers/Line Drivers with Inverting 3-State Outputs 16-PDIP -55 to 125 |
| 中文描述： | 128K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 151K |
| 代理商： | AT25F1024N-10SI-2.7 |
1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
20 MHz Clock Rate
Byte Mode and 256-byte Page Mode for Program Operations
Sector Architecture:
– Two Sectors with 32K Bytes Each (512K)
– Four Sectors with 32K Bytes Each (1M)
– 128 Pages per Sector
Product Identification Mode
Low-voltage Operation
– 2.7 (V
CC
= 2.7V to 3.6V)
Sector Write Protection
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Program Cycle (60 μs/Byte Typical)
Self-timed Sector Erase Cycle (1 second/Sector Typical)
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
– Endurance: 10,000 Write Cycles Typical
8-lead JEDEC SOIC
Description
The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash
memory organized as 65,536/131,072 words of 8 bits each. The device is optimized
for use in many industrial and commercial applications where low-power and low-volt-
age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead
JEDEC SOIC package.
The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or
entire memory array (512K) is enabled by programming the status register. Separate
write enable and write disable instructions are provided for additional data protection.
Hardware data protection is provided via the WP pin to protect against inadvertent
write attempts to the status register. The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
Rev. 1440M–SEEPR–7/03
SPI Serial
Memory
512K (65,536 x 8)
1M (131,072 x 8)
AT25F512
AT25F1024
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
相關PDF資料 |
PDF描述 |
|---|---|
| AT25F2048N-10SU-2.7 | 24 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| AT25F2048 | High Speed CMOS Logic Hex Buffers/Line Drivers with Inverting 3-State Outputs 16-SOIC -55 to 125 |
| AT25F2048N | High Speed CMOS Logic Hex Buffers/Line Drivers with Inverting 3-State Outputs 16-SOIC -55 to 125 |
| AT25F4096 | SPI SERIAL MEMORY 4M |
| AT25F4096W-10SU-2.7 | SPI SERIAL MEMORY 4M |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT25F1024N-10SU-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial Memory |
| AT25F1024Y4-10YU-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial Memory |
| AT25F2048 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial Memory 2M (262,144 x 8) |
| AT25F2048_07 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:2Mbit High Speed SPI Serial Flash Memory 2M (262,144 x 8) |
| AT25F2048N | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial Memory 2M (262,144 x 8) |
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