- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1902 > AT18F080-30XU (Atmel)IC FLASH CONFIG 7MBIT 20-TSSOP PDF資料下載
參數(shù)資料
| 型號： | AT18F080-30XU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLASH CONFIG 7MBIT 20-TSSOP |
| 產(chǎn)品變化通告： | AT18F Family Obsolescence 06/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 可編程類型： | 閃存 |
| 存儲容量： | 7Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 609 (CN2011-ZH PDF) |
7
3672A–CNFG–1/08
AT18F010/002/040/080 [Preliminary]
6.6
CEO
Chip Enable Output for configuration download. This output goes Low when the internal address
counter of the device has reached its maximum value which signals that all configuration data is
being clocked out of the device. In a daisy chain of AT18F Series devices, the CEO pin of one
device must be connected to the CE input of the next device in the chain. It will stay Low as long
as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay
High until the entire memory device is read again.
6.7
TMS
JTAG Mode Control Input. The state of TMS with the rising edge of TCK determines the state
transitions of the Test Access Port (TAP) controller. TMS has an internal 50 K
weak pull-up to
V
CCJ to provide a logic 1 to the device.
6.8
TCK
JTAG Clock Input. This pin is the JTAG clock input to the TAP controller of the device.
6.9
TDI
JTAG Serial Data Input. This pin is the serial input to all JTAG instructions and data registers. An
internal 50 K
weak pull-up to V
CCJ provides a logic 1 to the device.
6.10
TDO
JTAG Serial Data Output. This pin is the serial output to all JTAG instruction and data registers.
An internal 50 K
weak pull-up to V
CCJ provides a logic 1 to the device if the pin is not driven.
6.11
VCCINT
+3.3V supply voltage for internal logic.
6.12
NC
No Connect Pin. This pin is not connected to any internal logic of the device and can be left
floating.
6.13
VCCO
Supply voltage for I/O drivers (1.8V, 3.3V, or 3.3V).
6.14
VCCJ
Supply voltage for JTAG I/O drivers (1.8V, 3.3V, or 3.3V).
6.15
GND
Power supply ground.
7.
Standby Mode
The AT18F Series Configurators enter a low-power standby mode whenever the JTAG mode is
inactive and CE is asserted High. In this mode, the AT18F Configurator consumes less than 1
mA of current at 3.3V. The output remains in a high-impedance state regardless of the state of
the OE input.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT22LV10L-25SI | IC PLD EE 25NS LV UV 24-SOIC |
| AT32AP7000-CTUR | IC MCU AVR32 256-CTBGA |
| AT32AP7001-ALUT | IC MCU 32BIT AVR32 208-LQFP |
| AT32AP7002-CTUR | IC MCU AVR32 196-CBGA |
| AT32UC3A0512-ALUT | IC MCU AVR32 512KB FLASH 144LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT18F-DK3 | 功能描述:可編程邏輯 IC 開發(fā)工具 Development Kit for AT18F Series FPGAs RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| AT18V | 制造商:Apex Tool Group 功能描述:Wrench;Adjustable;1-1/8in.(29mm);8in. Long;Blk Phosphate Fin;Alloy Steel;Carded |
| AT18V8Z-25DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| AT18V8Z-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| AT18V8Z-25PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。