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參數(shù)資料
| 型號(hào)： | AS8501-ASOU |
| 廠商： | ams |
| 文件頁(yè)數(shù)： | 2/41頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DATA ACQ 16-SOIC |
| 特色產(chǎn)品： | AS8501 High Precision Data Acquisition Ics |
| 標(biāo)準(zhǔn)包裝： | 46 |
| 類(lèi)型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 輸入類(lèi)型： | 模擬，數(shù)字 |
| 輸出類(lèi)型： | 模擬，數(shù)字 |
| 接口： | 串行 |
| 電流 - 電源： | 5mA |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 803 (CN2011-ZH PDF) |
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AS8501 - Data Sheet
austriamicrosystems
Revision 1.1, 04-April-06
www.austriamicrosystems.com
Page 9 of 40
7
Functional Description
7.1
Power on Reset
The power on reset is iniciated during each power up of the ASSP and can be triggered purpously by reducing the analog supply voltage (VDDA) to a
value lower than Vporlo for a time interval longer than 0.5 sec.
During power on reset sequence the following steps are performed automatically:
-
The chip goes to mode MZL (see 7.4)
-
Internal clock is enabled
-
The calibration constants are loaded from Zener-zap memory to the appropriate registers (ZTR=>TRR, ZCL=>CAR). The load procedure is
directed by the internal clock and can be monitored on INTN pin. 188 clock pulses are generated from the internal oscillator source. Pulse period
is equal to internal clock period.
After the power-on reset sequence is finished:
-
the operation continues with internal clock if no external clock is detected. In this case the ASSPs switches to mode MWU with default value of
threshold register ( 214 )
-
If external clock is available the ASSP switches to mode current measurement MMS (default measurement with default configuration: gain=100,
fovs=4.096MHz, R1=64, MM=4, R2=1, NTH=214).
-
The microcontroller can communicate via SDI interface whenever appropriate, i.e. CAR and TRR register can be rewritten from the C if
necessary.
-
Because the automatic selected calibration factor (CGI4) is loaded with zeros, the ASSP delivers constant zero at the output to allow the C to
check for an unwanted POR. To bring the ASSP back into normal operation for current
measurement with gain100 the C has to copy the CAU4 content into the CGI4 factor in the CAR-register.
(see also 7.5.5 and 8.6.2)
7.2
Analog part, general description
The input signals are level shifted to AGND (+ 2.5 V) then switched by the special high quality MUX- which contains also the chopper – to the input of
the programmable gain amplifier (PGA). This low noise amplifier is optimised for best linearity, TC- value and speed at gain 24.
The systems contains an internal bandgap reference with high stability, low noise and low TC-value. The output of a programmable current source can
be switched to the analog inputs VBAT, ETS and ETR for testing the sensor connections
or for external activation of resistors, bridges or sensors (RTD, NTC). The voltage drop generated by the current is measured at the corresponding
input/output PIN.
For the wire break test of the RSHH and RSHL inputs special low noise current sources are implemented.
The integrated temperature sensor can also be switched to the PGA by the MUX and measured any time. The chip temperature can be used for the
temperature compensation of
the gain of the different channels in the external C, which increases the absolute accuracy considerably.
The offset of the amplifier itself is already fairly low, but to guarantee the full dynamic range it can be trimmed via the digital interface to nearly zero
independent of the autozero chopping function.
In the same way the manufacturing spread of the absolute value of the reference voltage can be eliminated and the TC-value set to nearly zero by a
trimming process via the SDI interface.
For more details of the input multiplexer see the following schematic. The position of all switches is defined by writing into the registers CRA, CRB and
CRG via the SDI bus, which is explained in 7.5.2 through 7.5.4.
INTERNAL
TEMPERA-
TURE
AD-
CON-
VERTER
PGA
AUXILIARY
CURRENT
SOURCE
M 12
M 13
M 3
M 10
M 14
CURRENT
SOURCE
M 2
M 1
M 4
M 15
M 8
M 7
M 9
M 6
ETR
ETS
VBAT
RSHH
RSHL
M 5
Figure 3: Multiplexer
ams
AG
Technical
content
still
valid
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