參數(shù)資料
型號(hào): AS5LC1008DJ-15/XT
廠商: AUSTIN SEMICONDUCTOR INC
元件分類: SRAM
英文描述: High-Speed CMOS SRAM with 3.3V Revolutionary Pinout
中文描述: 128K X 8 STANDARD SRAM, 15 ns, PDSO32
封裝: 0.400 INCH, PLASTIC, SOJ-32
文件頁數(shù): 5/10頁
文件大?。?/td> 521K
代理商: AS5LC1008DJ-15/XT
SRAM
AS5LC1008
AS5LC1008
Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
READ CYCLE SWITCHING CHARACTERISTICS1
(-55oC < T
A
< +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
NOTES:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1 output loading specified
in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
PARAMETER
UNIT
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output timing and Reference Levels
1.5V
Output Load
See Figures 1 and 2
FIGURE 1
FIGURE 2
AC TEST LOADS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Read Cycle Time
tRC
10
---
12
---
15
---
20
---
ns
Address Access Time
tAA
---
10
---
12
---
15
---
20
ns
Output Hold time
tOHA
2
---
2
---
2
---
2
---
ns
CE\ Access Time
tACE
---
10
---
12
---
15
---
20
ns
OE\ Access Time
tDOE
---
5
---
6
---
7
---
8
ns
OE\ to Low-Z Output
tLZOE
2
0
---
0
---
0
---
0
---
ns
OE\ to High-Z Output
tHZOE
2
05060708
ns
CE\ to Low-Z Output
tLZCE
2
---
2
---
2
---
2
---
ns
CE\ to High-Z Output
tHZCE
2
05060708
ns
-10
-12
-20
-15
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