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| 型號： | AS4C1M16F5-50TI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5V 1M X 16 CMOS DRAM |
| 中文描述： | 5V的100萬× 16的CMOS內(nèi)存 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 485K |
| 代理商： | AS4C1M16F5-50TI |
AS4C1M16F5
4/11/01; v.0.9.1
Alliance Semiconductor
P. 7 of 21
Notes
1
2
3
I
CC1
, I
CC3
, and I
CC4
are dependent on frequency.
I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
An initial pause of 200 μs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
AC Characteristics assume t
T
= 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V
IL
(min)
≥
GND and V
IH
(max)
≤
V
CC
.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and V
IL
.
Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by t
AA
.
Assumes three state test load (5 pF and a 380
Thevenin equivalent).
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10 t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
OFF
is referenced from
rising edge of RAS or CAS, whichever occurs last.
11 t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If t
WS
≥
t
WS
(min) and t
WH
≥
t
WH
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min) and t
AWD
≥
t
AWD
(min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
CAA
or t
CAC
or t
CPA
14 t
ASC
≥
t
CP
to achieve t
PC
(min) and t
CPA
(max) values.
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C1M16F5 5V devices.
4
5
6
7
8
9
AC test conditions
- Access times are measured with output reference levels
of V
OH
= 2.4V and V
OL
= 0.4V,
V
IH
IL
= 0.8V
- Input rise and fall times: 2 ns
Key to switching waveforms
Rising input
100 pF*
R2 = 295
R1 = 828
D
out
GND
+5V
Figure A: Equivalent output load
*including scope
and jig capacitance
Undefined output/don’t care
Falling input
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| AS4C1M16S-6TCN | 功能描述:IC SDRAM 16MBIT 166MHZ 50TSOP 制造商:alliance memory, inc. 系列:- 包裝:托盤 零件狀態(tài):在售 存儲器類型:易失 存儲器格式:DRAM 技術(shù):SDRAM 存儲容量:16Mb （1M x 16） 時鐘頻率:166MHz 寫周期時間 - 字，頁:2ns 訪問時間:5.4ns 存儲器接口:并聯(lián) 電壓 - 電源:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C（TA） 安裝類型:表面貼裝 封裝/外殼:50-TSOP（0.400"，10.16mm 寬） 供應(yīng)商器件封裝:50-TSOP II 標(biāo)準(zhǔn)包裝:117 |
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