
AS3515 V15
austriamicrosystems
Data Sheet, Confidential
www.austriamicrosystems.com
Revision 3.1
22
- 66
6.6.6
Parameter
Table 20 DAC/ADC Block Parameter
Symbol Parameter
Notes
Min
Typ
Max
Unit
programmable gain DAC input
-43.43
1.07
dB
A0
Gain
programmable gain ADC output
-34.5
12
dB
Ax
Gain Step-Size
1.5
dB
Gain Step-Precision
0.5
dB
Mute Attenuation
100
dB
I2S inputs / outputs
VIL
SCLK, LRCK, SDI (30%DVDD/2)
-
0.42
V
VIH
SCLK, LRCK, SDI (70%DVDD/2)
1.02
-
DVDD
V
VOL
SDO @ 2mA
-
0.3
V
VOH
SDO @ 2mA
2.6
-
V
tsu
Set-up Time
SDI versus high going edge of SCLK
80
ns
thd
Hold Time
SDI versus high going edge of SCLK
80
ns
ts1, ts2
Separation Time
SCLK high going edges separation from
LRCK edges
80
ns
tjitter
clock Jitter
LRCK
-20
20
ns
BVDD = 3.3V, DVDD = 2.9V, TA= 25oC unless otherwise mentioned
6.6.7
Register Description
Enabling the DAC or ADC is done via a control bit in the audio settings register (AudioSet1 register 0x14h). To get an interrupt on a LRCK
state change, the corresponding bit in the IRQ_ENRD1 register (0x25h) has to be set. Changing the bias current and adding a dither
signal is done via AudioSet2 register (0x15h). All other DAC or ADC settings are controlled by the following two registers.
Right DAC Register (0Eh)
Table 21 DAC_R Register
Bit
Name
Description
7..5
-
4..0
DAR_VOL
volume settings for right DAC input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
The register is R/W; default value is 00h
Left DAC Register (0Fh)
Table 22 DAC_R Register
Bit
Name
Description
7
-
6
DAC_Mute_off 0: DAC input is set to mute
1: normal operation
5
-
4..0
DAL_VOL
volume settings for left DAC input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
The register is R/W; default value is 00h
ams
AG
Technical
content
still
valid