參數(shù)資料
型號(hào)： AS3510
廠商： ams
文件頁(yè)數(shù)： 20/20頁(yè)
文件大?。?/td> 0K
描述： IC CODEC AFE ANALOG 49-CABGA
標(biāo)準(zhǔn)包裝： 476
類型： 音頻編解碼器
應(yīng)用： 便攜式音頻，電話
安裝類型： 表面貼裝
封裝/外殼： 49-WFBGA
供應(yīng)商設(shè)備封裝： 49-CSBGA（7x7）
包裝： 托盤
Product Brief AS3510
Rev. 1v2, June 2004
CONFIDENTIAL
Page 8 of 19
Supply Regulator
Block Description
This block can be used to provide three regulated supply
voltages for the
-
on_chip digital section
-
on_chip analog section
-
external circuit (uP, DSP…)
from the battery supply BVDD which is directly used by the
power_amplifier.
The LDO1 and LDO2 do have the capability to drive 50mA
with a voltage drop of <=50mV (1Ohm). Since the nominal
output voltage for these LDOs is 2.9V (+/-50mV), a
regulation can be done with BVDD as low as 3.0V.
The LDO3 is used to generate a supply voltage PVDD for
the peripheral cells and external digital circuits, which are
controlling the inputs of the AS3510. The drive capability is
≥200mA with a BVDD≥3V.
The maximum output currents for these LDOs can be
calculated using the following equation:
Ohm
mV
Vout
BVDD
I
1
50
)
(
max
+
=
Vout is 2.9V for LDO1 and LDO2. The output Voltage for
LDO3 can be programmed via the PLDO3 pin.
PLD3 pin
QLDO3 voltage
VSS
2.25V
150k to VSS
2.0V
open
2.5
150k to DVDD
1.5
DVDD
1.75
Table 10
LDO3 Programming
There are two pads at each LDO, one is the LDO output pad
and the second is the corresponding chip supply pad, which
are bonded to the same pin (LDO1 only), and have external
blocking caps (Cblock with low ESR).
If supply should not be generated from the on_chip LDOs,
these blocks can be disabled with control pin PowerUP.
AVDD, DVDD and PVDD can then be forced from external
regulators.
ams
AG
Technical
content
still
valid
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