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參數(shù)資料
| 型號： | AS3510 |
| 廠商： | ams |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC AFE ANALOG 49-CABGA |
| 標(biāo)準包裝： | 476 |
| 類型： | 音頻編解碼器 |
| 應(yīng)用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 49-WFBGA |
| 供應(yīng)商設(shè)備封裝： | 49-CSBGA（7x7） |
| 包裝： | 托盤 |
Product Brief AS3510
Rev. 1v2, June 2004
CONFIDENTIAL
Page 4 of 19
Inputs
Output
ADC-Modes
ENADC
I2S-Clocks
LRCK, SCLK,MCLK
MICP/MICN
SDO
OFF
L
X
static L
ADC_ON
H
LRCK up to 50kHz
MCLK … 128*F(LRCK)
SCLK … >=34*F(LRCK)
Differential analog
input
to be converted to
digital output
SDI serial data output
Ieft justified to LRCK with
MSB first at 2nd SCLK
edge
Table 3
ADC Operating Modes
Nodes:
-
There are 16bit presented at SDO at each cycle but just the first 14 do have relevalt data.
-
The ADC is a single channel (mono) path. The same SDO bitstream is presented for left and right channel of one cycle.
-
The ADC sampling rate is equal to LRCK/4. This means that the SDO bitstream gets updated at each 4th cycle of LRCK.
-
SCLK has to have at least 34 cycles within one LRCK cycle
2*(16bit data + the leading empty bit)
ams
AG
Technical
content
still
valid
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