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| 型號(hào)： | ARM720T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip |
| 中文描述： | 通用32位微處理器與8KB的高速緩存，擴(kuò)大寫入緩沖區(qū)和內(nèi)存管理單元（MMU）在單一芯片上結(jié)合 |
| 文件頁(yè)數(shù)： | 130/242頁(yè) |
| 文件大?。?/td> | 831K |
| 代理商： | ARM720T |
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Debug Interface
7-20
Copyright ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
Operating modes
The scan chains have three basic modes of operation, selected by the various TAP
controller instructions:
SYSTEM mode
The scan cells are idle. System data is applied to inputs, and core
outputs are applied to the system.
INTEST mode
The core is internally tested. The data serially scanned in is
applied to the core, and the resulting outputs are captured in the
output cells and scanned out.
EXTEST mode
Data is scanned onto the core outputs and applied to the external
system. System input data is captured in the input cells and then
shifted out.
Note
The scan cells are not fully JTAG-compliant because they do not have an update
stage. Therefore, while data is being moved around the scan chain, the contents
of the scan cell are not isolated from the output. Therefore the output from the
scan cell to the core or to the external system can change on every scan clock.
This does not affect ARM7TDM because its internal state does not change until
it is clocked. However, the rest of the system has to be aware that every output
can change asynchronously as data is moved around the scan chain. External
logic must ensure that this does not harm the rest of the system.
7.7.6
Scan chain 0
Scan chain 0 is intended primarily for inter-device testing (EXTEST), and testing the
core (INTEST). Scan chain 0 is selected using the SCAN_N instruction.
Serial testing the core
INTEST allows serial testing of the core. The TAP controller must be placed in INTEST
mode after scan chain 0 has been selected:
During CAPTURE-DR, the current outputs from the core logic are captured in
the output cells.
During SHIFT-DR, this captured data is shifted out while a new serial test
pattern is scanned in, applying known stimuli to the inputs.
During RUN-TEST-IDLE, the core is clocked. The TAP controller must only
spend one cycle in RUN-TEST-IDLE.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ARM7DIMM-LPC2478 | 功能描述:模塊化系統(tǒng) - SOM LPC2478 ARM7 DIMM Module, Rev 2.2 RoHS:否 制造商:Digi International 外觀尺寸:ConnectCore 9P 處理器類型:ARM926EJ-S 頻率:150 MHz 存儲(chǔ)容量:8 MB, 16 MB 存儲(chǔ)類型:NOR Flash, SDRAM 接口類型:I2C, SPI, UART 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 尺寸:1.97 in x 1.97 in x 6.1 in |
| ARM7TDI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
| ARM7TDMI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:general purpose 32-bit microprocessors |
| ARM7TDMI_G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
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