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| 型號： | ARD00354 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 24/50頁 |
| 文件大小： | 0K |
| 描述： | BOARD REF DESIGN MCP6N11/MCP6V2X |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 儀表 |
| 輸出類型： | 滿擺幅 |
| 電流 - 輸出 / 通道： | 30mA |
| 工作溫度： | -40°C ~ 125°C |
| 電流供應(yīng)（主 IC）： | 800µA |
| 板類型： | 完全填充 |
| 已供物品： | 板，線纜 |
| 已用 IC / 零件： | MCP6N11，MCP6001，MCP6V26，MCP6V27，PIC18F2553 |
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MCP6N11
DS25073A-page 30
2011 Microchip Technology Inc.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go too far above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
overvoltage (beyond VDD) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs.
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode-
connected FETs for low leakage.
FIGURE 4-5:
Protecting the Analog Inputs
Against High Voltages.
4.2.1.3
Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute Maxi-
mum Ratings ”). This requirement is independent of
the voltage limits previously discussed.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIP and VIM)
should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
4.2.1.4
Input Voltage Ranges
Figure 4-7 shows possible input voltage values
(VSS = 0V). Lines with a slope of +1 have constant VDM
(e.g., the VDM = 0 line). Lines with a slope of -1 have
constant VCM (e.g., the VCM =VDD/2 line).
For normal operation, VIP and VIM must be kept within
the region surrounded by the thick blue lines. The
horizontal and vertical blue lines show the limits on the
individual inputs. The blue lines with a slope of +1 show
the limits on VDM; the larger GMIN is, the closer they are
to the VDM = 0 line.
The input voltage range specs (VIVL and VIVH) change
with the supply voltages (VSS and VDD, respectively).
The differential input range specs (VDML and VDMH)
change with minimum gain (GMIN). Temperature also
affects these specs.
To take full advantage of VDML and VDMH, set VREF
(see Figure 1-6 and Figure 1-7) so that the output
(VOUT) is centered between the supplies (VSS and
VDD).
FIGURE 4-7:
Input Voltage Ranges.
VDD
V1
D1
V2
D2
U1
MCP6N11
min(R1,R2)>
VSS –min(V1,V2)
2mA
VDD
V1
R1
D1
V2
R2
D2
U1
MCP6N11
min(R1,R2) >
max(V1,V2)–VDD
2mA
VIP
VIM
V DM
=0
VIVH
VIVL
0
V
IV
H
V
IV
L
0
V D
M
=
V D
M
H
V
CM
=V
DD /2
V DM
=
V DM
H
VDD
V
DD
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