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參數(shù)資料
| 型號： | ARD00354 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD REF DESIGN MCP6N11/MCP6V2X |
| 標準包裝： | 1 |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 儀表 |
| 輸出類型： | 滿擺幅 |
| 電流 - 輸出 / 通道： | 30mA |
| 工作溫度： | -40°C ~ 125°C |
| 電流供應（主 IC）： | 800µA |
| 板類型： | 完全填充 |
| 已供物品： | 板，線纜 |
| 已用 IC / 零件： | MCP6N11，MCP6001，MCP6V26，MCP6V27，PIC18F2553 |
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2011 Microchip Technology Inc.
DS25073A-page 25
MCP6N11
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
3.1
Analog Signal Inputs
The non-inverting and inverting inputs (VIP, and VIM)
are high-impedance CMOS inputs with low bias
currents.
3.2
Analog Feedback Input
The analog feedback input (VFG) is the inverting input
of the second input stage. The external feedback
components (RF and RG) are connected to this pin. It is
a high-impedance CMOS input with low bias current.
3.3
Analog Reference Input
The analog reference input (VREF) is the non-inverting
input of the second input stage; it shifts VOUT to its
desired range. The external gain resistor (RG) is
connected to this pin. It is a high-impedance CMOS
input with low bias current.
3.4
Analog Output
The analog output (VOUT) is a low-impedance voltage
output. It represents the differential input voltage
(VDM =VIP –VIM), with gain GDM and is shifted by
VREF. The external feedback resistor (RF) is connected
to this pin.
3.5
Power Supply Pins
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply; VDD will
need bypass capacitors.
3.6
Digital Enable and VOS Calibration
Input
This input (EN/CAL) is a CMOS, Schmitt-triggered
input that controls the active, low power and VOS
calibration modes of operation. When this pin goes low,
the part is placed into a low power mode and the output
is high-Z. When this pin goes high, the amplifier’s input
offset voltage is corrected by the calibration circuitry,
then the output is re-connected to the VOUT pin, which
becomes low impedance, and the part resumes normal
operation.
3.7
Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (
θJA).
TABLE 3-1:
PIN FUNCTION TABLE
MCP6N11
Symbol
Description
SOIC
TDFN
11
VFG
Feedback Input
22
VIM
Inverting Input
33
VIP
Non-inverting Input
44
VSS
Negative Power Supply
55
VREF
Reference Input
66
VOUT
Output
77
VDD
Positive Power Supply
88
EN/CAL
Enable/VOS Calibrate Digital Input
—
9
EP
Exposed Thermal Pad (EP); must be connected to VSS
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