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參數(shù)資料
| 型號(hào)： | APL5325BI-TRG |
| 廠商： | ANPEC ELECTRONICS CORP |
| 元件分類： | 可調(diào)正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器 |
| 英文描述： | ADJUSTABLE POSITIVE LDO REGULATOR, PDSO5 |
| 封裝： | GREEN, TO-178AA, SOT-23, 5 PIN |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 259K |
| 代理商： | APL5325BI-TRG |
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Copyright
ANPEC Electronics Corp.
Rev. A.1 - Nov., 2008
APL5325
www.anpec.com.tw
10
Application Information
Where the unit of C
OUT
is
μ
F and V
OUT
is V. Figure 1 shows
the curve of maximum output capacitor over the output
voltage. The output voltage range is from 0.8 to 5.5V and
the output capacitor value should under the line. Output
capacitors must be placed at the load and the ground pin
as close as possible and the impedance of the layout
must be minimized.
P
D
= (T
J
- T
A
) /
JA
where (T
J
-T
A
) is the temperature difference between the
junction and ambient air.
between Junction and ambient air. Assuming the
T
A
=25
o
C and maximum T
J
=160
o
C (typical thermal limit
threshold), the maximum power dissipation is calcu-
lated as:
P
D(max)
=(160-25)/240
= 0.56(W)
For normal operation, do not exceed the maximum junc-
tion temperature rating of T
J
= 125
o
C. The calculated power
dissipation should less than:
P
D
=(125-25)/240
= 0.41(W)
The GND provides an electrical connection to the ground
and channels heat away. Connect the GND to the ground
by using a large pad or a ground plane.
JA
is the thermal resistance
O
μ
F
Output Voltage (V)
Figure 1
Input Capacitor
The APL5325 requires proper input capacitors to supply
surge current during stepping load transients to prevent
the input rail from dropping . Because the parasitic induc-
tor from the voltage sources or other bulk capacitors to
the VIN limit the slew rate of the surge current, place the
Input capacitors near VIN as close as possible. Input ca-
pacitors should be larger than 1
μ
F and a minimum ce-
ramic capacitor of 1
μ
F is necessary.
Output Capacitor
The APL5325 needs a proper output capacitor to main-
tain circuit stability and to improve transient response over
temperature and current. In order to insure the circuit
stability, the proper output capacitor value should be larger
than 2.2
μ
F With X5R and X7R dielectrics, 2.2
μ
F is suffi-
cient at all operating temperatures. Large output capaci-
tor value can reduce noise and improve load-transient
response and PSRR, however, it also affects power on
issue. Equation (1) shows the relationship between the
maximum C
OUT
value and the V
OUT
.
OUT
V
OUT(max)
19.5
101
C
=
0
1
2
3
4
5
6
60
70
80
90
100
110
120
Operation Region and Power Dissipation
The APL5325 maximum power dissipation depends on
the thermal resistance and temperature difference be-
tween the die junction and ambient air. The power dissi-
pation P
D
across the device is:
Layout Consideration
Figure 2 illustrates the layout. Below is a checklist for
your layout:
1. Please place the input capacitors close to the VIN.
2. Ceramic capacitors for load must be placed near the
load as close as possible.
3. To place APL5325 and output capacitors near the load
is good for performance.
4. Large current paths, the bold lines in figure 2, must
have wide tracks.
5. Divider resistor R1 and R2 must be placed near the
SET as close as possible.
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