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參數(shù)資料
| 型號： | APA600-CQ352B |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 108/178頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA PROASIC+ 600K 352-CQFP |
| 標準包裝： | 1 |
| 系列： | ProASICPLUS |
| RAM 位總計： | 129024 |
| 輸入/輸出數(shù)： | 248 |
| 門數(shù)： | 600000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-BFCQFP，帶拉桿 |
| 供應(yīng)商設(shè)備封裝： | 352-CQFP（75x75） |
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ProASICPLUS Flash Family FPGAs
v5.9
2-25
Design Environment
The ProASICPLUS family of FPGAs is fully supported by
both Actel's Libero Integrated Design Environment
(IDE) and Designer FPGA Development software. Actel
Libero IDE is an integrated design manager that
seamlessly integrates design tools while guiding the user
through the design flow, managing all design and log
files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment (see Actel’s
website for more information about Libero IDE). Libero
IDE includes Synplify AE from Synplicity, ViewDraw
AE from Mentor Graphics, ModelSim HDL Simulator
from Mentor Graphics, WaveFormer Lite AE from
SynaptiCAD, PALACE AE Physical Synthesis from
Magma, and Designer software from Actel.
PALACE is an effective tool when designing with
ProASICPLUS. PALACE AE Physical Synthesis from Magma
takes an EDIF netlist and optimizes the performance of
ProASICPLUS devices through a physical placement-driven
process, ensuring that timing closure is easily achieved.
Actel's Designer software is a place-and-route tool that
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
Timer – A world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
NetlistViewer – A design netlist schematic viewer
ChipPlanner – A graphical floorplanner viewer and
editor
SmartPower – Allows the designer to quickly
estimate the power consumption of a design
PinEditor – A graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor – Displays all assigned and
unassigned I/O macros and their attributes in a
spreadsheet format
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel’s back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the SmartGen
macro
builder,
which
easily
creates
popular
and
commonly used logic functions for implementation into
your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
ISP
The user can generate *.bit or *.stp programming files
from the Designer software and can use these files to
program a device.
ProASICPLUS devices can be programmed in-system. For
more information on ISP of ProASICPLUS devices, refer to
ProASICPLUS Devices application notes. Prior to being
programmed for the first time, the ProASICPLUS device I/Os
are in a tristate condition with the pull-up resistor option
enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| APA600-CQ352M | 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 600K GATES 180MHZ 0.22UM 2.5V 352CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 248 I/O 352CQFP |
| APA600-CQB | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA600-CQES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA600-CQGB | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA600-CQGES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
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