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寤犲晢锛� Microsemi SoC
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RAM 浣嶇附瑷堬細 73728
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ProASICPLUS Flash Family FPGAs
v5.9
2-11
The clock conditioning circuit can advance or delay the
clock up to 8 ns (in increments of 0.25 ns) relative to the
positive edge of the incoming reference clock. The system
also allows for the selection of output frequency clock
phases of 0掳 and 180掳.
Prior to the application of signals to the rib drivers, they
pass through programmable delay units, one per global
network. These units permit the delaying of global
signals relative to other signals to assist in the control of
input set-up times. Not all possible combinations of input
and output modes can be used. The degrees of freedom
available in the bidirectional global pad system and in
the clock conditioning circuit have been restricted. This
avoids unnecessary and unwieldy design kit and software
work.
Notes:
1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.
2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns.
3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.
Figure 2-11 PLL Block 鈥� Top-Level View and Detailed PLL Block Diagram
AVDD
AGND
GND
+
-
VDD
External Feedback Signal
GLA
GLB
Dynamic
Configuration Bits
Flash
Configuration Bits
8
27
4
Clock Conditioning
Circuitry
(Top level view)
Global MUX A OUT
Global MUX B OUT
See Figure 2-15
on page 2-15
Input Pins to the PLL
GLB
GLA
梅u
梅v
PLL Core
0掳
180掳
0
1
6
7
5
4
2
Delay Line 0.0 ns, 0.25 ns,
0.50 ns and 4.00 ns
P+
P-
Clock from Core
(GLINT mode)
CLK
1
0
Deskew
Delay
2.95 ns
1
2
3
Delay Line
0.25 ns to
4.00 ns,
16 steps,
0.25 ns
increments
3
1
2
Delay Line 0.0 ns, 0.25 ns,
0.50 ns and 4.00 ns
Clock from Core
(GLINT mode)
CLKA
EXTFB
XDLYSEL
Bypass Secondary
Bypass Primary
FIVDIV[4:0]
FBDIV[5:0]
FBSEL[1:0]
OAMUX[1:0]
DLYA[1:0]
DLYB[1:0]
OBDIV[1:0]
OBMUX[2:0]
OADIV[1:0]
FBDLY[3:0]
梅n
梅m
Clock Conditioning Circuitry Detailed Block Diagram
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APA300-FGG144 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 300K 144-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASICPLUS 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�