ProASICPLUS Flash Family FPGAs 2- 22 v5.9 Note: Each RAM block contains a mul" />
參數(shù)資料
型號： APA300-BGG456
廠商： Microsemi SoC
文件頁數(shù)： 105/178頁
文件大小： 0K
描述： IC FPGA PROASIC+ 300K 456-PBGA
標準包裝： 24
系列： ProASICPLUS
RAM 位總計： 73728
輸入/輸出數(shù)： 290
門數(shù)： 300000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 456-BBGA
供應商設備封裝： 456-PBGA（35x35）
ProASICPLUS Flash Family FPGAs
2- 22
v5.9
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 2-18 Example SRAM Block Diagrams
Table 2-14 Memory Block SRAM Interface Signals
SRAM Signal
Bits
In/Out
Description
WCLKS
1
In
Write clock used on synchronization on write side
RCLKS
1
In
Read clock used on synchronization on read side
RADDR<0:7>
8
In
Read address
RBLKB
1
In
Read block select (active Low)
RDB
1
In
Read pulse (active Low)
WADDR<0:7>
8
In
Write address
WBLKB
1
In
Write block select (active Low)
DI<0:8>
9
In
Input data bits <0:8>, <8> can be used for parity In
WRB
1
In
Write pulse (active Low)
DO<0:8>
9
Out
Output data bits <0:8>, <8> can be used for parity out
RPE
1
Out
Read parity error (active High)
WPE
1
Out
Write parity error (active High)
PARODD
1
In
Selects odd parity generation/detect when High, even parity when Low
Note: Not all signals shown are used in all modes.
SRAM
(256x9)
DI <0:8>
DO <0:8>
RADDR <0:7>
WADDR <0:7>
WRB
RDB
WBLKB
RBLKB
WCLKS
RCLKS
RPE
PARODD
DI <0:8>
WADDR <0:7>
WRB
WBLKB
PARODD
WPE
SRAM
(256x9)
DI <0:8>
DO <0:8>
WADDR <0:7>
WRB
RDB
WBLKB
RBLKB
WCLKS
RPE
PARODD
WPE
RADDR <0:7>
PARODD
DI <0:8>
DO <0:8>
RADDR <0:7>
WADDR <0:7>
WRB
RDB
WBLKB
RBLKB
RCLKS
RPE
WPE
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE
Sync Write
and
Sync Read
Ports
Async Write
and
Async Read
Ports
Sync Write
and
Async Read
Ports
Async Write
and
Sync Read
Ports
SRAM
(256x9)
SRAM
(256x9)
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相關代理商/技術參數(shù)
參數(shù)描述
APA300-BGG456I 功能描述:IC FPGA PROASIC+ 300K 456-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
APA300-BGG456M 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 456BGA - Trays
APA300-BGGB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA300-BGGES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA300-BGGI 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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