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鍨嬭櫉(h脿o)锛� APA150-TQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 57/178闋�
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ProASICPLUS Flash Family FPGAs
v5.9
2-5
Array Coordinates
During many place-and-route operations in Actel鈥檚
Designer software tool, it is possible to set constraints
that require array coordinates.
Table 2-2 is provided as a reference. The array coordinates
are measured from the lower left (0,0). They can be used in
region constraints for specific groups of core cells, I/Os, and
RAM blocks. Wild cards are also allowed.
I/O and cell coordinates are used for placement
constraints. Two coordinate systems are needed because
there is not a one-to-one correspondence between I/O
cells and core cells. In addition, the I/O coordinate system
changes depending on the die/package combination.
Core cell coordinates start at the lower left corner
(represented as (1,1)) or at (1,5) if memory blocks are
present at the bottom. Memory coordinates use the
same system and are indicated in Table 2-2. The memory
coordinates for an APA1000 are illustrated in Figure 2-5.
For more information on how to use constraints, see the
Designer User鈥檚 Guide or online help for ProASICPLUS
software tools.
Table 2-2
Array Coordinates
Device
Logic Tile
Memory Rows
All
Min.
Max.
Bottom
Top
xy
x
y
Min.
Max.
APA075
1
96
32
鈥�
(33,33) or (33, 35)
0,0
97, 37
APA150
1
128
48
鈥�
(49,49) or (49, 51)
0,0
129, 53
APA300
1
5
128
68
(1,1) or (1,3)
(69,69) or (69, 71)
0,0
129, 73
APA450
1
5
192
68
(1,1) or (1,3)
(69,69) or (69, 71)
0,0
193, 73
APA600
1
5
224
100
(1,1) or (1,3)
(101,101) or (101, 103)
0,0
225, 105
APA750
1
5
256
132
(1,1) or (1,3)
(133,133) or (133, 135)
0,0
257, 137
APA1000
1
5
352
164
(1,1) or (1,3)
(165,165) or (165, 167)
0,0
353, 169
Figure 2-5 Core Cell Coordinates for the APA1000
(353,169)
(352,167)
(352,165)
(352,164)
(352,5)
(352,3)
(353,0)
(352,1)
(1,5)
(1,1)
(1,164)
(1,165)
(1,3)
(1,167)
(1,169)
(0,0)
Core
Memory
Blocks
Memory
Blocks
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APA150-TQ100I IC FPGA PROASIC+ 150K 100-TQFP
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