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鍨嬭櫉锛� APA150-TQ100A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 150/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 150K 100-TQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 66
闁€鏁�(sh霉)锛� 150000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 100-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-TQFP锛�14x14锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-63
Asynchronous Write and Read to the Same Location
Note: The plot shows the normal operation status.
Figure 2-36 Asynchronous Write and Read to the Same Location
Table 2-60 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 鈥�55掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
ORDA
New DO access from RB
鈫�
7.5
ns
ORDH
Old DO valid from RB
鈫�
3.0
ns
OWRA
New DO access from WB
鈫�
3.0
ns
OWRH
Old DO valid from WB
鈫�
0.5
ns
RAWRS
RB
鈫� or RADDR from WB 鈫�
5.0
ns
RAWRH
RB
鈫� or RADDR from WB 鈫�
5.0
ns
Notes:
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically
trigger a read operation which updates the read data. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more
information.
2. Violation or RAWRS will disturb access to the OLD data.
3. Violation of RAWRH will disturb access to the NEWER data.
RB, RADDR
OLD
NEWER
NEW
t
ORDA
t
ORDH
t
OWRH
t
RAWRH
WB = {WRB+WBLKB}
DO
t
OWRA
t
RAWRS
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