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ProASICPLUS Flash Family FPGAs
2- 64
v5.9
Synchronous Write and Asynchronous Read to the Same Location
Note: The plot shows the normal operation status.
Figure 2-37 Synchronous Write and Asynchronous Read to the Same Location
Table 2-61 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 鈥�55掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
ORDA
New DO access from RB
鈫�
7.5
ns
ORDH
Old DO valid from RB
鈫�
3.0
ns
OWRA
New DO access from WCLKS
鈫�
3.0
ns
OWRH
Old DO valid from WCLKS
鈫�
0.5
ns
RAWCLKS
RB
鈫� or RADDR from WCLKS 鈫�
5.0
ns
RAWCLKH
RB
鈫� or RADDR from WCLKS 鈫�
5.0
ns
Notes:
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically
trigger a read operation which updates the read data.
2. Violation of RAWCLKS will disturb access to OLD data.
3. Violation of RAWCLKH will disturb access to NEWER data.
RB, RADDR
OLD
NEWNEWER
t
ORDA
t
ORDH
t
RAWCLKS
t
RAWCLKH
WCLKS
DO
t
OWRH
t
OWRA