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鍨嬭櫉锛� APA1000-FGG896
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 24/178闋�
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鎻忚堪锛� IC FPGA PROASIC+ 1M 896-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 27
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 202752
杓稿叆/杓稿嚭鏁�(sh霉)锛� 642
闁€鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 896-BGA
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ProASICPLUS Flash Family FPGAs
2- 2
v5.9
Figure 2-2 Efficient Long-Line Resources
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Logic Cell
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Spans 2 Tiles
Spans 4 Tiles
Logic Tile
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
24C00-I/ST IC EEPROM 128BIT 400KHZ 8TSSOP
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APA1000-FGG896A 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 1M 896-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:352-CQFP锛�75x75锛�
APA1000-FGG896I 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 1M 896-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:352-CQFP锛�75x75锛�
APA1000-FGG896M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 896-Pin FBGA 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 896FBGA - Trays
APA1000-FGGB 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA1000-FGGES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs