ProASICPLUS Flash Family FPGAs v5.9 2-45 OB33PL 3.3V, High Output Current, Low S" />
參數(shù)資料
型號: APA075-PQ208A
廠商: Microsemi SoC
文件頁數(shù): 130/178頁
文件大小: 0K
描述: IC FPGA PROASIC+ 75K 208-PQFP
標準包裝: 24
系列: ProASICPLUS
RAM 位總計: 27648
輸入/輸出數(shù): 158
門數(shù): 75000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
ProASICPLUS Flash Family FPGAs
v5.9
2-45
OB33PL
3.3V, High Output Current, Low Slew Rate
2.7
3.5
ns
OB33LH
3.3V, Low Output Current, High Slew Rate
2.7
4.3
ns
OB33LN
3.3V, Low Output Current, Nominal Slew Rate
3.3
4.7
ns
OB33LL
3.3V, Low Output Current, Low Slew Rate
3.3
6.1
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
Table 2-34 Worst-Case Military Conditions
VDDP = 2.3 V, VDD = 2.3V, 35 pF load, TJ = 125°C for Military/MIL-STD-883
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Units
Std.
OB25LPHH
2.5V, Low Power, High Output Current, High Slew Rate3
2.3
2.4
ns
OB25LPHN
2.5V, Low Power, High Output Current, Nominal Slew Rate3
2.7
3.3
ns
OB25LPHL
2.5V, Low Power, High Output Current, Low Slew Rate3
3.2
3.5
ns
OB25LPLH
2.5V, Low Power, Low Output Current, High Slew Rate3
3.0
5.0
ns
OB25LPLN
2.5V, Low Power, Low Output Current, Nominal Slew Rate3
3.9
4.6
ns
OB25LPLL
2.5V, Low Power, Low Output Current, Low Slew Rate3
4.3
5.7
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. Low power I/O work with VDDP = 2.5 V ±10% only. VDDP = 2.3 V for delays.
Table 2-33 Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 125°C for Military/MIL-STD-883
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Units
Std.
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